LAN9353 Datasheet, PDF (90/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Bits
Description
Type
4
IRQ Polarity (IRQ_POL)
R/W
When cleared, this bit enables the IRQ line to function as an active low out-
NASR
put. When set, the IRQ output is active high. When the IRQ is configured as _{Note 1}
an open-drain output (via the IRQ_TYPE bit), this bit is ignored and the inter-
rupt is always active low.
0: IRQ active low output
1: IRQ active high output
3:2 RESERVED
RO
1
IRQ Clock Select (IRQ_CLK_SELECT)
R/W
When this bit is set, the crystal clock may be output on the IRQ pin. This is
intended to be used for system debug purposes in order to observe the clock
and not for any functional purpose.
Default
0b
-
0b
Note: When using this bit, the IRQ pin should be set to a push-pull driver.
0
IRQ Buffer Type (IRQ_TYPE)
R/W
0b
When this bit is cleared, the IRQ pin functions as an open-drain output for
NASR
use in a wired-or interrupt configuration. When set, the IRQ is a push-pull
Note 1
driver.
Note: When configured as an open-drain output, the IRQ_POL bit is
ignored and the interrupt output is always active low.
0: IRQ pin open-drain output
1: IRQ pin push-pull driver
Note 1: Register bits designated as NASR are not reset when the DIGITAL_RST bit in the Reset Control Register
(RESET_CTL) is set.
DS00001925A-page 90
 2015 Microchip Technology Inc.