LAN9353 Datasheet, PDF (81/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 7-2: HARD-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
turbo_mii_enable_strap_0
Description
Pins
Switch Port 0 Turbo MII Enable Strap: Configures the
default value of the Turbo Mode Enable bit in the (x=0) Port
x Virtual PHY Special Control/Status Register (VPHY_SPE-
CIAL_CONTROL_STATUS_x) when in MII PHY mode.
P0_MODE1
P1_mode_strap[2:0]
0 = 100Mbps
1 = 200Mbps
See Table 7-3 for the combined Port 0 mode strapping.
Switch Port 1 Mode Strap: Configures the mode of opera-
tion for Port 1.
000 = (reserved )
001 = (reserved )
010 = RMII MAC Mode
011 = RMII PHY Mode
100 = Internal PHY
P1_INTPHY :
P1_MODE3 :
P1_MODE2
These operating modes result from the following mapping:
P1_INTPHY
(see note)
0
0
1
P1_MODE[2] P1_mode_strap[2:0]
0
010 (RMII MAC)
1
011 (RMII PHY)
x
100 (Internal PHY)
Note: P1_INTPHY equal to 0 forces RMII remapping
mode which forces Port 1 into RMII mode.
See Table 7-4 for the combined Port 1 mode strapping.
P1_rmii_clock_dir_strap
Switch Port 1 RMII Clock Direction Strap: Configures the
default value of the RMII Clock Direction bit in the (x=1) Port
x Virtual PHY Special Control/Status Register (VPHY_SPE-
CIAL_CONTROL_STATUS_x).
P1_MODE1
0 = Input
1 = Output
See Table 7-4 for the combined Port 1 mode strapping.
 2015 Microchip Technology Inc.
DS00001925A-page 81