LAN9353 Datasheet, PDF (105/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
the MII Management Data (MDIO) signal and the MII Management Clock (MDC) signal. These signals allow access to
all PHY registers. Refer to Section 9.2.20, "Physical PHY Registers," on page 120 for a list of all supported registers
and register descriptions. Non-supported registers will be read as FFFFh.
9.2.9 PHY INTERRUPTS
The PHY contains the ability to generate various interrupt events. Reading the PHY x Interrupt Source Flags Register
(PHY_INTERRUPT_SOURCE_x) shows the source of the interrupt. The PHY x Interrupt Mask Register (PHY_INTER-
RUPT_MASK_x) enables or disables each PHY interrupt.
The PHY Management Control block aggregates the enabled interrupts status into an internal signal which is sent to
the System Interrupt Controller and is reflected via the Physical PHY A Interrupt Event (PHY_INT_A) and Physical PHY
B Interrupt Event (PHY_INT_B) bits of the Interrupt Status Register (INT_STS). For more information on the device inter-
rupts, refer to Section 8.0, "System Interrupts," on page 84.
The PHY interrupt system provides two modes, a Primary interrupt mode and an Alternative interrupt mode. Both modes
will assert the internal interrupt signal sent to the System Interrupt Controller when the corresponding mask bit is set.
These modes differ only in how they de-assert the internal interrupt signal. These modes are detailed in the following
subsections.
Note: The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative
interrupt mode requires setup after a power-up or hard reset.
9.2.9.1 Primary Interrupt Mode
The Primary interrupt mode is the default interrupt mode. The Primary interrupt mode is always selected after power-up
or hard reset. In this mode, to enable an interrupt, set the corresponding mask bit in the PHY x Interrupt Mask Register
(PHY_INTERRUPT_MASK_x) (see Table 9-3). When the event to assert an interrupt is true, the internal interrupt signal
will be asserted. When the corresponding event to de-assert the interrupt is true, the internal interrupt signal will be de-
asserted.
TABLE 9-3: INTERRUPT MANAGEMENT TABLE
Mask
30.9
30.8
30.7
30.6
Interrupt Source Flag
29.9 Link Up
29.8 Wake on LAN
29.7 ENERGYON
29.6 Auto-Negotia-
tion complete
Interrupt Source
Event to Assert
interrupt
Event to
De-assert interrupt
LINKSTAT Link Status
See Note 1
Rising LINK-
STAT
Falling LINKSAT or
Reading register 29
WOL_INT Enabled
See Note 2 WOL event
Rising WOL_INT Falling WOL_INT or
Reading register 29
17.1
ENERGYON Rising 17.1
Falling 17.1 or
(Note 3)
Reading register 29
1.5
Auto-Negoti- Rising 1.5
Falling 1.5 or
ate Com-
Reading register 29
plete
 2015 Microchip Technology Inc.
DS00001925A-page 105