LAN9353 Datasheet, PDF (187/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.3.5.1 Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x)
Offset:
PORT0: 1C0h
PORT1: 0C0h
Index (decimal): 0
Size:
This read/write register is used to configure the Virtual PHY.
32 bits
16 bits
Bits
Description
31:16 RESERVED
(See Note 37)
15 Reset (VPHY_RST)
When set, this bit resets the Virtual PHY registers to their default state. This
bit is self clearing.
0: Normal Operation
1: Reset
14 Loopback (VPHY_LOOPBACK)
This bit enables/disables the loopback mode. When enabled, transmissions
from the external MAC are not sent to the Switch Fabric. Instead, they are
looped back onto the receive path.
0: Loopback mode disabled (normal operation)
1: Loopback mode enabled
13 Speed Select LSB (VPHY_SPEED_SEL_LSB)
This bit is used to set the speed of the Virtual PHY when the Auto-Negotia-
tion (VPHY_AN) bit is disabled.
0: 10 Mbps
1: 100/200 Mbps
12 Auto-Negotiation (VPHY_AN)
This bit enables/disables Auto-Negotiation. When enabled, the Speed Select
LSB (VPHY_SPEED_SEL_LSB) and Duplex Mode (VPHY_DUPLEX) bits
are overridden.
0: Auto-Negotiation disabled
1: Auto-Negotiation enabled
This bit is also used when in external MAC modes to override the duplex and
speed (for RMII MAC mode) indication from the external PHY. When this bit
is set, the duplex and speed are determined by the input pins. When this bit
is cleared, the duplex is determined by the Duplex Mode (VPHY_DUPLEX)
bit and the speed is determined by the Speed Select LSB (VPHY_-
SPEED_SEL_LSB) bit.
11 Power Down (VPHY_PWR_DWN)
This bit is not used by the Virtual PHY and has no effect.
Type
RO
R/W
SC
R/W
R/W
R/W
R/W
Default
-
0b
0b
0b
1b
0b
 2015 Microchip Technology Inc.
DS00001925A-page 187