LAN9353 Datasheet, PDF (37/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-13: CORE AND I/O POWER PIN DESCRIPTIONS
Num
Pins
Name
Regulator
1 +3.3 V Power
Supply
+1.8 V to +3.3 V
5
Variable I/O
Power
+1.2 V Digital
3
Core Power
Supply
1
pad
Ground
Symbol
VDD33
VDDIO
VDDCR
VSS
Buffer
Type
P
P
Description
+3.3 V power supply for internal regulators. See
Note 13.
Note: +3.3 V must be supplied to this pin even
if the internal regulators are disabled.
+1.8 V to +3.3 V variable I/O power. See Note 13.
Supplied by the on-chip regulator unless configured
for regulator off mode via REG_EN.
P
1 µF and 470 pF decoupling capacitors in parallel to
ground should be used on pin 6. See Note 13.
P
Common ground. This exposed pad must be con-
nected to the ground plane with a via array.
Note 13: Refer to Section 4.0, "Power Connections," on page 38, the device reference schematic, and the device
LANCheck schematic checklist for additional connection information.
 2015 Microchip Technology Inc.
DS00001925A-page 37