LAN9353 Datasheet, PDF (272/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.2.25 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)
Register #:
Port0: 0440h
Port1: 0840h
Port2: 0C40h
Size:
32 bits
This read/write register configures the transmit packet parameters of the port.
Bits
Description
31:9 RESERVED
8
Energy Efficient Ethernet (EEE_ENABLE)
When set, this bit enables EEE operation (both TX LPI and RX LPI)
Type
RO
R/W
7
MAC Counter Test
R/W
When set, TX and RX counters that normally clear to 0 when read, will be set
to 7FFF_FFFCh when read with the exception of the Port x MAC Receive
Packet Length Count Register (MAC_RX_PKTLEN_CNT_x), Port x MAC
Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x) and
Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOOD-
PKTLEN_CNT_x) counters which will be set to 7FFF_FF80h.
6:2 IFG Config
R/W
These bits control the transmit inter-frame gap.
IFG bit times = (IFG Config * 4) + 12
Note: IFG Config values less than 15 are unsupported.
1
TX Pad Enable
R/W
When set, transmit packets shorter than 64 bytes are padded with zeros and
will become 64 bytes in length.
Note:
Padding is used when a VLAN tagged frame of less than 68 bytes
is received and has its tag removed (becoming less than 64 bytes
in length).
Default
-
Note 18
0b
10101b
1b
0
TX Enable (TXEN)
R/W
1b
When set, the transmit port is enabled. When cleared, the transmit port is dis-
abled.
Note 18: The default value of this field is determined by the EEE_enable_strap_0, EEE_enable_strap_1 or EEE_en-
able_strap_2 configuration strap.
DS00001925A-page 272
 2015 Microchip Technology Inc.