LAN9353 Datasheet, PDF (106/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 9-3: INTERRUPT MANAGEMENT TABLE (CONTINUED)
30.5
29.5 Remote Fault
1.4
Detected
Remote
Fault
Rising 1.4
30.4
29.4 Link Down
1.2
Link Status Falling 1.2
30.3
29.3 Auto-Negotia-
5.14
tion LP Acknowl-
edge
30.2
29.2 Parallel Detec- 6.4
tion Fault
Acknowl-
edge
Parallel
Detection
Fault
Rising 5.14
Rising 6.4
30.1
29.1 Auto-Negotia-
6.1
tion Page
Received
Page
Received
Rising 6.1
Falling 1.4, or
Reading register 1 or
Reading register 29
Reading register 1 or
Reading register 29
Falling 5.14 or
Reading register 29
Falling 6.4 or
Reading register 6, or
Reading register 29, or
Re-Auto Negotiate or
Link down
Falling 6.1 or
Reading register 6, or
Reading register 29, or
Re-Auto Negotiate, or
Link down.
Note 1: LINKSTAT is the internal link status and is not directly available in any register bit.
Note 2: WOL_INT is defined as bits 7:4 in the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) ANDed
with bits 3:0 of the same register, with the resultant 4 bits OR’ed together.
Note 3: If the mask bit is enabled and the internal interrupt signal has been de-asserted while ENERGYON is still
high, the internal interrupt signal will assert for 256 ms, approximately one second after ENERGYON goes
low when the Cable is unplugged. To prevent an unexpected assertion of the internal interrupt signal, the
ENERGYON interrupt mask should always be cleared as part of the ENERGYON interrupt service routine.
Note:
The Energy On (ENERGYON) bit in the PHY x Mode Control/Status Register (PHY_MODE_CON-
TROL_STATUS_x) is defaulted to a ‘1’ at the start of the signal acquisition process, therefore the INT7 bit
in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will also read as a ‘1’ at
power-up. If no signal is present, then both Energy On (ENERGYON) and INT7 will clear within a few mil-
liseconds.
9.2.9.2 Alternate Interrupt Mode
The Alternate interrupt mode is enabled by setting the ALTINT bit of the PHY x Mode Control/Status Register (PHY_-
MODE_CONTROL_STATUS_x) to “1”. In this mode, to enable an interrupt, set the corresponding bit of the in the PHY
x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) (see Table 9-4). To clear an interrupt, clear the interrupt source
and write a ‘1’ to the corresponding Interrupt Source Flag. Writing a ‘1’ to the Interrupt Source Flag will cause the state
machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If the con-
DS00001925A-page 106
 2015 Microchip Technology Inc.