LAN9353 Datasheet, PDF (343/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Figure 11-3 illustrates a typical single and multiple register read.
FIGURE 11-3:
I²C SLAVE READS
S
S
A
6
Control Byte
SSSSSS
AAAAAA
543210
0
A
C
K
A
9
Address Byte
AAAAAA
876543
A
2
A
C
K
S
S
A
6
Control Byte
SSSSSS
AAAAAA
543210
1
A
C
K
D
3
1
Data Byte
DDDSD
32222
09876
D
2
5
D
2
4
A
C
K
... ^{Data Byte... ...Data Byte}
DDDD
2222
3210
DDDDD
54321
D
0
A
C
K
P
R/~W
Single Register Read
S
S
A
6
Control Byte
SSSSSS
AAAAAA
543210
0
A
C
K
A
9
Address Byte
AAAAAA
876543
A
2
A
C
K
S
S
A
6
Control Byte
SSSSSS
AAAAAA
543210
1
A
C
K
... ^{Data 1 Byte}
DD
33
DD
22
10
54
...^{...Data m Byte}
A
C
K
DDDD
4321
D
0
A
C
K
... ^{Data m+1 Byte... ...Data n Byte}
DDDDDD
332222
109876
DDDD
4321
D
0
A
C
K
P
R/~W
Multiple Register Reads
SPECIAL CSR HANDLING
Live Bits
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read to prevent the
host from reading an intermediate value. The latching occurs multiple times in a multiple read sequence.
Change on Read Registers and FIFOs
Any register that is affected by a read operation (e.g. a clear on read bit) is cleared once the host has acknowledge the
3rd byte of output (an acknowledge of the 3rd byte indicates that the host will read the fourth byte). Since the full 32-bits
of the register were saved at the beginning of the read, the 4th byte of data that is output is the original value and not
the updated value.
In the event that the host sends a no-acknowledge on one of the first three bytes or a start or stop condition occurs
unexpectedly before the acknowledge of the 3rd byte, the read is considered invalid and the register is not affected.
Multiple registers may be cleared in a multiple read cycle, each one being cleared as it is read.
Change on Read Live Register Bits
As described above, the current value from a register with live bits (as is the case of any register) is saved before the
data is shifted out. Although a H/W event that occurs following the data capture would still update the live bit(s), the live
bit(s) will be affected (cleared, etc.) once the output shift has started and the H/W event would be lost. In order to prevent
this, the individual CSRs defer the H/W event update until after the read indication.
11.3.5 I²C SLAVE WRITE SEQUENCE
Following the device addressing, as detailed in Section 11.3.1, a register is written to the device when the master con-
tinues to send data bytes. Each byte is acknowledged by the device. Following the fourth byte of the sequence, the mas-
ter may either send another start condition or halt the sequence with a stop condition. The internal register address is
unchanged following a single write.
Multiple writes are performed when the master sends additional bytes following the fourth acknowledge. The internal
address is automatically incremented and the next register is written. Once the internal address reaches its maximum
value, it rolls over to 0. The multiple write is concluded when the master sends another start or stop condition. The inter-
nal register address is incremented for each write including the final. This is not relevant for subsequent writes, since a
new register address would be included on a new write cycle. However, this does affect the internal register address if
it were to be used for reads without first resetting the register address.
For both single and multiple writes, if the master sends an unexpected start or stop condition, the device will stop imme-
diately and will respond to the next sequence as needed.
The data write to the register occurs after the 32 bits are input. In the event that 32 bits are not written (master sends a
start or a stop condition occurs unexpectedly), the write is considered invalid and the register is not affected. Multiple
registers may be written in a multiple write cycle, each one being written after 32 bits. I²C writes must not be performed
to unused register addresses.
 2015 Microchip Technology Inc.
DS00001925A-page 343