LAN9353 Datasheet, PDF (98/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 9-2: 4B/5B CODE TABLE (CONTINUED)
Code Group
Sym
Receiver Interpretation
Transmitter Interpretation
01000
01100
10000
/V/
INVALID, MII Receive Error (RXER) if
INVALID
during MII Receive Data Valid (RXDV)
/V/
INVALID, MII Receive Error (RXER) if
INVALID
during MII Receive Data Valid (RXDV)
/V/
INVALID, MII Receive Error (RXER) if
INVALID
during MII Receive Data Valid (RXDV)
9.2.2.3 Scrambler and PISO
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band
peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire
channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being
radiated by the physical wiring.
The seed for the scrambler is generated from the PHY address, ensuring that each PHY will have its own scrambler
sequence. For more information on PHY addressing, refer to Section 9.1.1, "PHY Addressing".
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
9.2.2.4 NRZI and MLT-3 Encoding
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI
data stream. The NRZI is then encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents
a code bit “1” and the logic output remaining at the same level represents a code bit “0”.
9.2.2.5 100M Transmit Driver
The MLT-3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal on output pins TXPx
and TXNx, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-T and 100BASE-TX signals
pass through the same transformer so that common “magnetics” can be used for both. The transmitter drives into the
100  impedance of the CAT-5 cable. Cable termination and impedance matching require external components.
9.2.2.6 100M Phase Lock Loop (PLL)
The 100M PLL locks onto the reference clock and generates the 125 MHz clock used to drive the 125 MHz logic and
the 100BASE-TX Transmitter.
DS00001925A-page 98
 2015 Microchip Technology Inc.