LAN9353 Datasheet, PDF (452/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.26 1588 PORT X RX FILTER CONFIGURATION REGISTER (1588_RX_FILTER_CONFIG_X)
Offset:
Bank:
168h
1
Size:
32 bits
This register is used to configure PTP message filtering.
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). The port
accessed (“x”) is set by the Port Select (PORT_SEL[1:0]) field.
Bits
Description
31:19
18
17
16
15:0
RESERVED
RX PTP Alternate Master Filter Enable
(RX_PTP_ALT_MASTER_FLTR_EN)
This bit enables message filtering based on the alternateMasterFlag flagField
bit.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
RX PTP Domain Filter Enable (RX_PTP_DOMAIN_FLTR_EN)
This bit enables message filtering based on the PTP domain.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
RX PTP Version Filter Enable (RX_PTP_VERSION_FLTR_EN)
This bit enables message filtering based on the PTP version.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
RX PTP Message Type Filter Enable (RX_PTP_MSG_FLTR_EN[15:0])
These bits enable individual message filtering. Bit 0 of this field corresponds
to a message type value of 0 (Sync), bit 1 to message type value 1
(Delay_Req), etc.
Typically Delay_Req and Delay_Resp messages are filtered for peer-to-peer
transparent clocks.
Type
RO
R/W
R/W
R/W
R/W
Default
-
0b
0b
0b
0000h
DS00001925A-page 452
 2015 Microchip Technology Inc.