LAN9353 Datasheet, PDF (434/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.13 1588 CLOCK TARGET X NANOSECONDS REGISTER (1588_CLOCK_TARGET_NS_X)
Offset:
Bank:
Channel A: 130h
Channel B: 140h
Channel A: na
Channel B: na
Size:
32 bits
This read/write register combined with 1588 Clock Target x Seconds Register (1588_CLOCK_TARGET_SEC_x) form
the 1588 Clock Target value. The 1588 Clock Target value is compared to the current 1588 Clock value and can be used
to trigger an interrupt upon at match. Refer to Section 15.4, "1588 Clock Events" for additional information.
Bits
Description
31:30
29:0
RESERVED
Clock Target NanoSeconds (CLOCK_TARGET_NS)
This field contains the nanoseconds portion of the 1588 Clock Compare
value.
Type
RO
R/W
Default
-
00000000h
Note:
Note:
Note:
Both this register and the 1588 Clock Target x Seconds Register (1588_CLOCK_TARGET_SEC_x) must
be written for either to be affected.
The value read is the saved value of the 1588 Clock Target when the Clock Target Read
(1588_CLOCK_TARGET_READ) bit in the 1588 Command and Control Register (1588_CMD_CTL) is set.
When the Clock Target Read (1588_CLOCK_TARGET_READ) bit is set, the previous value written to this
register is overwritten. Normally, a read command should not be requested in between writing this register
and the 1588 Clock Target x Seconds Register (1588_CLOCK_TARGET_SEC_x).
DS00001925A-page 434
 2015 Microchip Technology Inc.