LAN9353 Datasheet, PDF (29/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-7: SWITCH PORT 1 RMII & CONFIGURATION STRAP PIN DESCRIPTIONS
Num
Pins
Name
Symbol
Port 1 RMII
Output Data 0
1
Port 1 Mode[1]
Configuration
Strap
P1_OUTD0
P1_MODE1
Port 1 RMII
1
Output Data
Valid
P1_OUTDV
Port 1 Speed
P1_SPEED
Buffer
Type
VO8
VO8
-
VIS
(PU)
Note 11
VO8
VO8
-
VIS
(PU)
Description
RMII MAC Mode: This pin is the transmit data 0 bit
from the switch to the external PHY.
RMII PHY Mode: This pin is the receive data 0 bit
from the switch to the external MAC. The output
driver is disabled when the Isolate (VPHY_ISO) bit
is set in the Port 1 Port x Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL_x).
Internal PHY Mode: This pin is not used.
This strap configures the mode for Port 1. See
Note 10.
Refer to Table 7-4, “Port 1 Mode Strap Mapping,” on
page 83 for the Port 1 strap settings.
RMII MAC Mode: This pin is the TX_EN signal to
the external PHY.
RMII PHY Mode: This pin is the CRS_DV signal to
the external MAC. The output driver is disabled
when the Isolate (VPHY_ISO) bit is set in the Port 1
Port x Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL_x).
Internal PHY Mode: This pin is not used.
RMII MAC Mode: This pin can be changed at any
time (live value) and is typically tied to the speed
indication from the external PHY. It can be overrid-
den by the Speed Select LSB (VPHY_-
SPEED_SEL_LSB) bit in the Port 1 Port x Virtual
PHY Basic Control Register (VPHY_BASIC_C-
TRL_x) by clearing the Auto-Negotiation
(VPHY_AN) bit in the same register.
1
Port 1
Management
Data
Input/Output
-
P1_MDIO
-
VIS/VO8
(PD)
The polarity of this pin is determined by the
speed_pol_strap_1.
RMII PHY Mode: This is the management data to/
from an external master and is used to access port
1’s Virtual PHY.
Note:
An external pull-up is required when the
MII management interface is used, to
ensure that the IDLE state of the MDIO
signal is a logic one.
Note:
To avoid a floating signal, an external
pull-up is recommended when the MII
management interface is not used.
Internal PHY Mode: This pin is not used.
 2015 Microchip Technology Inc.
DS00001925A-page 29