LAN9353 Datasheet, PDF (86/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
The following sections detail each category of interrupts and their related registers. Refer to the corresponding function’s
chapter for bit-level definitions of all interrupt registers.
8.2.1 1588 INTERRUPTS
Multiple 1588 Time Stamp interrupt sources are provided by the device. The top-level 1588 Interrupt Event
(1588_EVNT) bit of the Interrupt Status Register (INT_STS) provides indication that a 1588 interrupt event occurred in
the 1588 Interrupt Status Register (1588_INT_STS).
The 1588 Interrupt Enable Register (1588_INT_EN) provides enabling/disabling of all 1588 interrupt conditions. The
1588 Interrupt Status Register (1588_INT_STS) provides the status of all 1588 interrupts. These include TX/RX 1588
clock capture indication on Ports 2,1,0, 1588 clock capture for GPIO events, as well as 1588 timer interrupt indication.
In order for a 1588 interrupt event to trigger the external IRQ interrupt pin, the desired 1588 interrupt event must be
enabled in the 1588 Interrupt Enable Register (1588_INT_EN), bit 29 (1588_EVNT_EN) of the Interrupt Enable Register
(INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the of the Interrupt Con-
figuration Register (IRQ_CFG).
For additional details on the 1588 Time Stamp interrupts, refer to Section 15.0, "IEEE 1588," on page 394.
8.2.2 SWITCH FABRIC INTERRUPTS
Multiple Switch Fabric interrupt sources are provided by the device in a three-tiered register structure as shown in
Figure 8-1. The top-level Switch Fabric Interrupt Event (SWITCH_INT) bit of the Interrupt Status Register (INT_STS)
provides indication that a Switch Fabric interrupt event occurred in the Switch Global Interrupt Pending Register
(SW_IPR).
The Switch Global Interrupt Pending Register (SW_IPR) and Switch Global Interrupt Mask Register (SW_IMR) provide
status and enabling/disabling of all Switch Fabric sub-modules interrupts (Buffer Manager, Switch Engine and Port 2,1,0
MACs).
The low-level Switch Fabric sub-module interrupt pending and mask registers of the Buffer Manager, Switch Engine and
Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-modules. These low-level registers provide
the following interrupt sources:
• Buffer Manager (Buffer Manager Interrupt Mask Register (BM_IMR) and Buffer Manager Interrupt Pending Reg-
ister (BM_IPR))
- Status B Pending
- Status A Pending
• Switch Engine (Switch Engine Interrupt Mask Register (SWE_IMR) and Switch Engine Interrupt Pending Regis-
ter (SWE_IPR))
- Interrupt Pending
• Port 2,1,0 MACs (Port x MAC Interrupt Mask Register (MAC_IMR_x) and Port x MAC Interrupt Pending Register
(MAC_IPR_x))
- No currently supported interrupt sources. These registers are reserved for future use.
In order for a Switch Fabric interrupt event to trigger the external IRQ interrupt pin, the following must be configured:
• The desired Switch Fabric sub-module interrupt event must be enabled in the corresponding mask register (Buffer
Manager Interrupt Mask Register (BM_IMR) for the Buffer Manager, Switch Engine Interrupt Mask Register
(SWE_IMR) for the Switch Engine and/or Port x MAC Interrupt Mask Register (MAC_IMR_x) for the Port 2,1,0
MACs)
• The desired Switch Fabric sub-module interrupt event must be enabled in the Switch Global Interrupt Mask Regis-
ter (SW_IMR)
• The Switch Engine Interrupt Event Enable (SWITCH_INT_EN) bit of the Interrupt Enable Register (INT_EN) must
be set
• The IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register
(IRQ_CFG)
8.2.3 ETHERNET PHY INTERRUPTS
The Ethernet PHYs each provide a set of identical interrupt sources. The top-level Physical PHY A Interrupt Event
(PHY_INT_A) and Physical PHY B Interrupt Event (PHY_INT_B) bits of the Interrupt Status Register (INT_STS) provide
indication that a PHY interrupt event occurred in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_-
SOURCE_x).
DS00001925A-page 86
 2015 Microchip Technology Inc.