LAN9353 Datasheet, PDF (33/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-10: GPIO, LED & CONFIGURATION STRAP PIN DESCRIPTIONS (CONTINUED)
Num
Pins
Name
LED 5
1
General
Purpose I/O 5
PHY Address
Configuration
Strap
LED 4
1
General
Purpose I/O 4
1588 Enable
Configuration
Strap
Symbol
LED5
GPIO5
PHYADD
LED4
GPIO4
1588EN
Buffer
Type
Description
VO12/
VOD12/
VOS12
This pin is configured to operate as an LED when
the LED 5 Enable bit of the LED Configuration Reg-
ister (LED_CFG) is set. The buffer type depends on
the setting of the LED Function 2-0 (LED_FUN[2:0])
field in the LED Configuration Register (LED_CFG)
and is configured to be either a push-pull or open-
drain/open-source output. When selected as an
open-drain/open-source output, the polarity of this
pin depends upon the PHYADD strap value sam-
pled at reset.
Note: Refer to Section 17.3, "LED Operation,"
on page 486 to additional information.
This pin is configured to operate as a GPIO when
the LED 5 Enable bit of the LED Configuration Reg-
VIS/VO12/
VOD12
(PU)
ister (LED_CFG) is clear. The pin is fully program-
mable as either a push-pull output, an open-drain
output or a Schmitt-triggered input by writing the
General Purpose I/O Configuration Register (GPI-
O_CFG) and the General Purpose I/O Data & Direc-
tion Register (GPIO_DATA_DIR).
VIS
(PU)
This strap configures the default value of the Switch
PHY Address Select soft-strap. See Note 12.
VO12/
VOD12/
VOS12
This pin is configured to operate as an LED when
the LED 4 Enable bit of the LED Configuration Reg-
ister (LED_CFG) is set. The buffer type depends on
the setting of the LED Function 2-0 (LED_FUN[2:0])
field in the LED Configuration Register (LED_CFG)
and is configured to be either a push-pull or open-
drain/open-source output. When selected as an
open-drain/open-source output, the polarity of this
pin depends upon the 1588EN strap value sampled
at reset.
Note: Refer to Section 17.3, "LED Operation,"
on page 486 to additional information.
This pin is configured to operate as a GPIO when
the LED 4 Enable bit of the LED Configuration Reg-
VIS/VO12/
VOD12
(PU)
ister (LED_CFG) is clear. The pin is fully program-
mable as either a push-pull output, an open-drain
output or a Schmitt-triggered input by writing the
General Purpose I/O Configuration Register (GPI-
O_CFG) and the General Purpose I/O Data & Direc-
tion Register (GPIO_DATA_DIR).
VIS
(PU)
This strap configures the default value of the 1588
Enable soft-strap. See Note 12.
 2015 Microchip Technology Inc.
DS00001925A-page 33