LAN9353 Datasheet, PDF (188/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Bits
Description
10 Isolate (VPHY_ISO)
This bit controls the MII/RMII input/output pins. When set and in MII/RMII
PHY mode, the output pins are not driven, pull-ups and pull-downs are dis-
abled and the input pins are powered down and ignored. When in MAC
mode, this bit is ignored and has no effect. (Note 38)
Type
R/W
Default
0b
0: Non-Isolated (Normal operation)
1: Isolated
9
Restart Auto-Negotiation (VPHY_RST_AN)
When set, this bit updates the emulated Auto-Negotiation results.
R/W
0b
SC
0: Normal operation
1: Auto-Negotiation restarted
8
Duplex Mode (VPHY_DUPLEX)
R/W
0b
This bit is used to set the duplex when the Auto-Negotiation (VPHY_AN) bit
is disabled.
0: Half Duplex
1: Full Duplex
7
Collision Test (VPHY_COL_TEST)
R/W
0b
This bit enables/disables the collision test mode. When set, the collision sig-
nal to the external MAC is active during transmission from the MAC.
Note: It is recommended that this bit be used only when in loopback
mode.
0: Collision test mode disabled
1: Collision test mode enabled
6
Speed Select MSB (VPHY_SPEED_SEL_MSB)
RO
0b
This bit is not used by the Virtual PHY and has no effect. The value returned
is always 0.
5:0 RESERVED
RO
-
Note 37: The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD bound-
ary. When accessed serially (through the MII management protocol), the register is 16-bits wide.
Note 38: The isolation does not apply to the MII management pins (MDIO).
DS00001925A-page 188
 2015 Microchip Technology Inc.