LAN9353 Datasheet, PDF (35/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-10: GPIO, LED & CONFIGURATION STRAP PIN DESCRIPTIONS (CONTINUED)
Num
Pins
Name
Symbol
Buffer
Type
Description
LED 1
LED1
VO12/
VOD12/
VOS12
This pin is configured to operate as an LED when
the LED 1 Enable bit of the LED Configuration Reg-
ister (LED_CFG) is set. The buffer type depends on
the setting of the LED Function 2-0 (LED_FUN[2:0])
field in the LED Configuration Register (LED_CFG)
and is configured to be either a push-pull or open-
drain/open-source output. When selected as an
open-drain/open-source output, the polarity of this
pin depends upon the P1_INTPHY strap value sam-
pled at reset.
Note: Refer to Section 17.3, "LED Operation,"
on page 486 to additional information.
1
General
Purpose I/O 1
GPIO1
This pin is configured to operate as a GPIO when
the LED 1 Enable bit of the LED Configuration Reg-
VIS/VO12/
VOD12
(PU)
ister (LED_CFG) is clear. The pin is fully program-
mable as either a push-pull output, an open-drain
output or a Schmitt-triggered input by writing the
General Purpose I/O Configuration Register (GPI-
O_CFG) and the General Purpose I/O Data & Direc-
tion Register (GPIO_DATA_DIR).
Port 1 Internal
PHY Mode
Configuration
Strap
P1_INTPHY
VIS
(PU)
This strap is used in configuring the mode for Ports
0 and 1. See Note 12.
Refer to Table 7-3, “Port 0 Mode Strap Mapping,”
on page 83 and Table 7-4, “Port 1 Mode Strap
Mapping,” on page 83 for the Port 0 and 1 strap
settings.
LED 0
LED0
VO12/
VOD12/
VOS12
This pin is configured to operate as an LED when
the LED 0 Enable bit of the LED Configuration Reg-
ister (LED_CFG) is set. The buffer type depends on
the setting of the LED Function 2-0 (LED_FUN[2:0])
field in the LED Configuration Register (LED_CFG)
and is configured to be either a push-pull or open-
drain/open-source output. When selected as an
open-drain/open-source output, the polarity of this
pin depends upon the MNGT0 strap value sampled
at reset.
1
General
Purpose I/O 0
GPIO0
Note: Refer to Section 17.3, "LED Operation,"
on page 486 to additional information.
This pin is configured to operate as a GPIO when
the LED 0 Enable bit of the LED Configuration Reg-
VIS/VO12/
VOD12
(PU)
ister (LED_CFG) is clear. The pin is fully program-
mable as either a push-pull output, an open-drain
output or a Schmitt-triggered input by writing the
General Purpose I/O Configuration Register (GPI-
O_CFG) and the General Purpose I/O Data & Direc-
tion Register (GPIO_DATA_DIR).
Host Interface
Configuration
Strap 0
MNGT0
VIS
(PU)
This strap configures the value of the Serial
Management Mode hard-strap.
Note 12: Configuration strap pins are identified by an underlined symbol name. Configuration strap values are
latched on power-on reset or RST# de-assertion. Refer to Section 7.0, "Configuration Straps," on page 67
for more information.
 2015 Microchip Technology Inc.
DS00001925A-page 35