LAN9353 Datasheet, PDF (440/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.19 1588 PORT X LATENCY REGISTER (1588_LATENCY_X)
Offset:
Bank:
158h
0
Size:
32 bits
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). The port
accessed (“x”) is set by the Port Select (PORT_SEL[1:0]) field.
Bits
Description
31:16
TX Latency (TX_LATENCY[15:0])
This field specifies the egress delay in nanoseconds between the PTP time-
stamp point and the network medium. The setting is used to adjust the inter-
nally captured 1588 clock value such that the resultant timestamp more
accurately corresponds to the start of the frame’s first symbol after the SFD
on the network medium.
The value depends on the port mode. Typical values are:
• 100BASE-TX: 95ns
• 100BASE-FX: 68ns plus the receive latency of the fiber transceiver
• 10BASE-T: 1139ns
• 100Mbps MII: 20ns plus any external receive latency
• 10Mbps MII: 380ns plus any external receive latency
• 200Mbps TMII: 0ns plus any external receive latency
• 100Mbps RMII: 20ns plus any external receive latency
• 10Mbps RMII: 20ns plus any external receive latency
Note:
The host S/W must not change this field while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
15:0 RX Latency (RX_LATENCY[15:0])
This field specifies the ingress delay in nanoseconds between the network
medium and the PTP timestamp point. The setting is used to adjust the inter-
nally captured 1588 clock value such that the resultant timestamp more accu-
rately corresponds to the start of the frame’s first symbol after the SFD on the
network medium.
The value depends on the port mode. Typical values are:
• 100BASE-TX: 285ns
• 100BASE-FX: 231ns plus the receive latency of the fiber transceiver
• 10BASE-T: 1674ns
• 100Mbps MII: 20ns plus any external receive latency
• 10Mbps MII: 20ns plus any external receive latency
• 200Mbps TMII: 20ns plus any external receive latency
• 100Mbps RMII: 70ns plus any external receive latency
• 10Mbps RMII: 440ns plus any external receive latency
Note:
The host S/W must not change this field while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
Type
R/W
R/W
Default
20 for Port 0
Note 2
95 for Port 1
Note 3
95 for Port 2
Note 4
20 for Port 0
Note 2
285 for Port 1
Note 3
285 for Port 2
Note 4
DS00001925A-page 440
 2015 Microchip Technology Inc.