LAN9353 Datasheet, PDF (22/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-6: SWITCH PORT 0 MII/RMII & CONFIGURATION STRAP PIN DESCRIPTIONS
Num
Pins
Name
Symbol
1
Port 0 MII
Input Clock
P0_INCLK
1
Port 0 MII
Output Data 3
P0_OUTD3
Port 0 MII
Output Data 2
1
P0_OUTD2
Port 0 Mode[3]
Configuration
Strap
P0_MODE3
Buffer
Type
VIS
(PD)
VO12/
VO16
Note 6
-
VO8
VO8
-
VO8
VO8
-
VIS
(PU)
Note 8
Description
MII MAC Mode: This pin is an input and is used as
the reference clock for the P0_IND[3:0], P0_INER
and P0_INDV pins. It is connected to the receive
clock of the external PHY.
MII PHY Mode: This pin is an output and is used as
the reference clock for the P0_IND[3:0], P0_INER
and P0_INDV pins. It is connected to the transmit
clock of the external MAC. The output driver is dis-
abled when the Isolate (VPHY_ISO) bit is set in the
Port 0 Port x Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL_x). When operating at
200 Mbps, the choice of drive strength is based on
the setting of the RMII/Turbo MII Clock Strength bit
in the Port 0 Port x Virtual PHY Special Control/Sta-
tus Register (VPHY_SPECIAL_CONTROL_STA-
TUS_x). A low selects a 12 mA drive, while a high
selects a 16 mA drive.
RMII MAC and RMII PHY Modes: This pin is not
used.
MII MAC Mode: This pin is the transmit data 3 bit
from the switch to the external PHY.
MII PHY Mode: This pin is the receive data 3 bit
from the switch to the external MAC. The output
driver is disabled when the Isolate (VPHY_ISO) bit
is set in the Port 0 Port x Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL_x).
RMII MAC and RMII PHY Modes: This pin is not
used.
MII MAC Mode: This pin is the transmit data 2 bit
from the switch to the external PHY.
MII PHY Mode: This pin is the receive data 2 bit
from the switch to the external MAC. The output
driver is disabled when the Isolate (VPHY_ISO) bit
is set in the Port 0 Port x Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL_x).
RMII MAC and RMII PHY Modes: This pin is not
used.
This strap configures the mode for Port 0. See
Note 7.
Refer to Table 7-3, “Port 0 Mode Strap Mapping,” on
page 83 for the Port 0 strap settings.
DS00001925A-page 22
 2015 Microchip Technology Inc.