LAN9353 Datasheet, PDF (62/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
For both automatic and manual wake-up, the Device Ready (READY) bit will go high once the device is returned to
power savings state D0 and the PLL has re-stabilized. The PM_MODE and PM_SLEEP_EN fields in the Power Man-
agement Control Register (PMT_CTRL) will also clear at this point.
Under normal conditions, the device will wake-up within 2 ms.
6.3.5
6.3.5.1
POWER MANAGEMENT REGISTERS
Power Management Control Register (PMT_CTRL)
Offset:
084h
Size:
32 bits
This read-write register controls the power management features of the device. The ready state of the device be deter-
mined via the Device Ready (READY) bit of this register.
Note:
This register can be read while the device is in the reset or not ready / power savings states without leaving
the host interface in an intermediate state. If the host interface is in a reset state, returned data may be
invalid.
It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register.
Bits
Description
31:29
Power Management Mode (PM_MODE)
This register field determines the chip level power management mode that
will be entered when the Power Management Sleep Enable
(PM_SLEEP_EN) bit is set.
000: D0
001: D1
010: D2
011: D3
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Writes to this field are ignored if Power Management Sleep Enable
(PM_SLEEP_EN) is also being written with a 1.
This field is cleared when the device wakes up.
Type
R/W/SC
Default
000b
DS00001925A-page 62
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