LAN9353 Datasheet, PDF (89/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
8.3.1 INTERRUPT CONFIGURATION REGISTER (IRQ_CFG)
Offset:
054h
Size:
32 bits
This read/write register configures and indicates the state of the IRQ signal.
Bits
Description
31:24
Interrupt De-assertion Interval (INT_DEAS)
This field determines the Interrupt Request De-assertion Interval in multiples
of 10 microseconds.
Setting this field to zero causes the device to disable the INT_DEAS Interval,
reset the interval counter and issue any pending interrupts. If a new, non-zero
value is written to this field, any subsequent interrupts will obey the new set-
ting.
Type
R/W
23:15 RESERVED
RO
14 Interrupt De-assertion Interval Clear (INT_DEAS_CLR)
R/W
Writing a 1 to this register clears the de-assertion counter in the Interrupt
SC
Controller, thus causing a new de-assertion interval to begin (regardless of
whether or not the Interrupt Controller is currently in an active de-assertion
interval).
0: Normal operation
1: Clear de-assertion counter
13 Interrupt De-assertion Status (INT_DEAS_STS)
RO
When set, this bit indicates that the interrupt controller is currently in a de-
assertion interval and potential interrupts will not be sent to the IRQ pin.
When this bit is clear, the interrupt controller is not currently in a de-assertion
interval and interrupts will be sent to the IRQ pin.
0: Interrupt controller not in de-assertion interval
1: Interrupt controller in de-assertion interval
12 Master Interrupt (IRQ_INT)
RO
This read-only bit indicates the state of the internal IRQ line, regardless of the
setting of the IRQ_EN bit, or the state of the interrupt de-assertion function.
When this bit is set, one of the enabled interrupts is currently active.
0: No enabled interrupts active
1: One or more enabled interrupts active
11:9 RESERVED
RO
8
IRQ Enable (IRQ_EN)
R/W
This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ
output is disabled and permanently de-asserted. This bit has no effect on any
internal interrupt status bits.
0: Disable output on IRQ pin
1: Enable output on IRQ pin
7:5 RESERVED
RO
Default
00h
-
0h
0b
0b
-
0b
-
 2015 Microchip Technology Inc.
DS00001925A-page 89