LAN9353 Datasheet, PDF (353/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
12.4 EEPROM Loader
The EEPROM Loader interfaces to the I²C EEPROM controller, the PHYs and to the system CSRs (via the Register
Access MUX). All system CSRs are accessible to the EEPROM Loader.
The EEPROM Loader runs upon a pin reset (RST#), power-on reset (POR), digital reset (Digital Reset (DIGITAL_RST)
bit in the Reset Control Register (RESET_CTL)) or upon the issuance of a RELOAD command via the EEPROM Com-
mand Register (E2P_CMD). Refer to Section 6.2, "Resets," on page 51 for additional information on resets.
The EEPROM contents must be loaded in a specific format for use with the EEPROM Loader. An overview of the
EEPROM content format is shown in Table 12-3. Each section of EEPROM contents is discussed in detail in the follow-
ing sections.
TABLE 12-3: EEPROM CONTENTS FORMAT OVERVIEW
EEPROM Address
0
1
2
3
4
5
6
7
8 - 16
17
18
19 and above
Description
EEPROM Valid Flag
MAC Address Low Word [7:0]
MAC Address Low Word [15:8]
MAC Address Low Word [23:16]
MAC Address Low Word [31:24]
MAC Address High Word [7:0]
MAC Address High Word [15:8]
Configuration Strap Values Valid Flag
Configuration Strap Values
Burst Sequence Valid Flag
Number of Bursts
Burst Data
Value
A5h
1^st Byte on the Network
2^nd Byte on the Network
3^rd Byte on the Network
4^th Byte on the Network
5^th Byte on the Network
6^th Byte on the Network
A5h
See Table 12-4
A5h
See Section 12.4.5, "Register
Data"
See Section 12.4.5, "Register
Data"
12.4.1 EEPROM LOADER OPERATION
Upon a pin reset ((RST#), power-on reset (POR), digital reset (Digital Reset (DIGITAL_RST) bit in the Reset Control
Register (RESET_CTL)) or upon the issuance of a RELOAD command via the EEPROM Command Register
(E2P_CMD), the EEPROM Controller Busy (EPC_BUSY) bit in the EEPROM Command Register (E2P_CMD) will be
set. While the EEPROM Loader is active, the Device Ready (READY) bit of the Hardware Configuration Register
(HW_CFG) is cleared and no writes to the device should be attempted. The operational flow of the EEPROM Loader
can be seen in Figure 12-8.
 2015 Microchip Technology Inc.
DS00001925A-page 353