LAN9353 Datasheet, PDF (123/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.1 PHY x Basic Control Register (PHY_BASIC_CONTROL_x)
Index (decimal): 0
This read/write register is used to configure the PHY.
Size:
16 bits
Bits
Description
15 Soft Reset (PHY_SRST)
When set, this bit resets all the PHY registers to their default state, except
those marked as NASR type. This bit is self clearing.
0: Normal operation
1: Reset
14 Loopback (PHY_LOOPBACK)
This bit enables/disables the loopback mode. When enabled, transmissions
are not sent to network. Instead, they are looped back into the PHY.
0: Loopback mode disabled (normal operation)
1: Loopback mode enabled
13 Speed Select LSB (PHY_SPEED_SEL_LSB)
This bit is used to set the speed of the PHY when the Auto-Negotiation
Enable (PHY_AN) bit is disabled.
0: 10 Mbps
1: 100 Mbps
12 Auto-Negotiation Enable (PHY_AN)
This bit enables/disables Auto-Negotiation. When enabled, the Speed Select
LSB (PHY_SPEED_SEL_LSB) and Duplex Mode (PHY_DUPLEX) bits are
overridden.
This bit is forced to a 0 if the 100BASE-FX Mode (FX_MODE) bit of the PHY
x Special Modes Register (PHY_SPECIAL_MODES_x) is a high.
0: Auto-Negotiation disabled
1: Auto-Negotiation enabled
11 Power Down (PHY_PWR_DWN)
This bit controls the power down mode of the PHY.
0: Normal operation
1: General power down mode
10 RESERVED
9
Restart Auto-Negotiation (PHY_RST_AN)
When set, this bit restarts the Auto-Negotiation process.
0: Normal operation
1: Auto-Negotiation restarted
Type
R/W
SC
R/W
R/W
R/W
R/W
RO
R/W
SC
Default
0b
0b
Note 8
Note 9
0b
-
0b
 2015 Microchip Technology Inc.
DS00001925A-page 123