LAN9353 Datasheet, PDF (183/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Note:
In MAC modes, the Virtual PHY registers are accessible through their memory mapped registers via the SMI
or I²C serial management interfaces only. The Virtual PHY registers are not accessible through MII man-
agement.
9.3.2.1 Duplex
In the MAC modes of operation, if the Auto-Negotiation (VPHY_AN) of the Port x Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL_x) is set, the duplex is based on the Px_DUPLEX pin and duplex_pol_strap_x (duplex-
_pol_strap_0 for Virtual PHY 0, duplex_pol_strap_1 for Virtual PHY 1) configuration strap. If these signals are equal,
the switch fabric MAC is configured for full-duplex, otherwise it is set for half-duplex. The Px_DUPLEX pin is typically
connected to the duplex indication of the external PHY. The duplex is not latched since the Auto-Negotiation process is
not used.
The duplex can be manually selected by clearing the Auto-Negotiation (VPHY_AN) bit and controlling the Duplex Mode
(VPHY_DUPLEX) bit in the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x).
9.3.2.2 Speed
In the RMII MAC mode of operation, if the Auto-Negotiation (VPHY_AN) of the Port x Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL_x) is set, the speed is based on the Px_SPEED pin and speed_pol_strap_x (speed_pol_strap_0
for Virtual PHY 0, speed_pol_strap_1 for Virtual PHY 1) configuration strap. If these signals are equal, the switch fabric
is configured for 100Mbps, otherwise it is set for 10Mbps. The Px_SPEED pin is typically connected to the speed indi-
cation of the external PHY. The speed is not latched since the Auto-Negotiation process is not used.
The speed can be manually selected by clearing the Auto-Negotiation (VPHY_AN) bit and controlling the Speed Select
LSB (VPHY_SPEED_SEL_LSB) bit in the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x).
Note: In the MAC MII mode of operation, the speed is controlled by the rate of the MII clocks from the PHY and
not by any register bits or configuration input pins.
9.3.2.3 Full-Duplex Flow Control
In the MAC modes of operation, full-duplex flow control should be controlled manually by the host via the Port 0 Manual
Flow Control Register (MANUAL_FC_0) (or Port 1 Manual Flow Control Register (MANUAL_FC_1)), based on the
external PHYs Auto-Negotiation results.
9.3.3 VIRTUAL PHY RESETS
In addition to the chip-level hardware reset (RST#) and Power-On Reset (POR), block specific resets are supported.
These are is discussed in the following sections. For detailed information on all device resets, refer to Section 6.2,
"Resets," on page 51.
9.3.3.1 Virtual PHY Software Reset via RESET_CTL
The Virtual PHYs can be reset via the Reset Control Register (RESET_CTL) by setting the Virtual PHY 0 Reset
(VPHY_0_RST) or Virtual PHY 1 Reset (VPHY_1_RST) bit. This bit is self clearing after approximately 102 us.
9.3.3.2 Virtual PHY Software Reset via VPHY_BASIC_CTRL
The Virtual PHY can also be reset by setting the Reset (VPHY_RST) bit 15 of the Port x Virtual PHY Basic Control Reg-
ister (VPHY_BASIC_CTRL_x). This bit is self clearing and will return to 0 after the reset is complete.
 2015 Microchip Technology Inc.
DS00001925A-page 183