LAN9353 Datasheet, PDF (285/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.2.49 Port x MAC Interrupt Mask Register (MAC_IMR_x)
Register #:
Port0: 0480h
Port1: 0880h
Port2: 0C80h
Size:
32 bits
This register contains the Port x interrupt mask. Port x related interrupts in the Port x MAC Interrupt Pending Register
(MAC_IPR_x) may be masked via this register. An interrupt is masked by setting the corresponding bit of this register.
Clearing a bit will unmask the interrupt. Refer to Section 8.0, "System Interrupts," on page 84 for more information.
Note: There are no possible Port x interrupt conditions available. This register exists for future use and should be
configured as indicated for future compatibility.
Bits
Description
31:8 RESERVED
7:0 RESERVED
Note: These bits must be written as 11h.
10.7.2.50 Port x MAC Interrupt Pending Register (MAC_IPR_x)
Type
RO
R/W
Default
-
11h
Register #:
Port0: 0481h
Port1: 0881h
Port2: 0C81h
Size:
32 bits
This read-only register contains the pending Port x interrupts. A set bit indicates an interrupt has been triggered. All inter-
rupts in this register may be masked via the Port x MAC Interrupt Pending Register (MAC_IPR_x) register. Refer to Sec-
tion 8.0, "System Interrupts," on page 84 for more information.
Note: There are no possible Port x interrupt conditions available. This register exists for future use.
Bits
31:0 RESERVED
Description
Type
RO
Default
-
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DS00001925A-page 285