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| LAN9353 Datasheet, PDF (184/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII | |||
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LAN9353
9.3.4 VIRTUAL PHY TIMING REQUIREMENTS
FIGURE 9-9:
VIRTUAL PHY TIMING
MDC
tval
tohold
MDIO
(Data-Out)
tclkp
tclkh tclkl
tohold
MDIO
(Data-In)
tsu tihold
TABLE 9-20: VIRTUAL PHY TIMING VALUES
Symbol
Description
Min
Max
tclkp
MDC period
400
-
tclkh
MDC high time
160 (80%)
-
tclkl
MDC low time
160 (80%)
-
tval
MDIO output valid from rising edge of MDC
-
300
tohold
MDIO output hold from rising edge of MDC
10
-
tsu
MDIO input setup time to rising edge of MDC
10
-
tihold
MDIO input hold time after rising edge of MDC
5
-
Units
ns
ns
ns
ns
ns
ns
ns
Notes
Note 6
Note 6
Note 7
Note 7
Note 35: The Virtual PHY design changes output data a nominal 4 clocks (100MHz) maximum and a nominal 2 clocks
(100MHz) minimum following the rising edge of MDC.
Note 36: The Virtual PHY design samples input data using the rising edge of MDC.
DS00001925A-page 184
ï£ 2015 Microchip Technology Inc.
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