LAN9353 Datasheet, PDF (200/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.3.5.8
Port x Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS_x)
Offset:
PORT0: 1DCh
PORT1: 0DCh
Index (decimal): 31
Size:
32 bits
16 bits
This read/write register contains a current link speed/duplex indicator and SQE control.
Bits
31:16 RESERVED
(See Note 64)
15 Mode[2]
See Mode[1:0] below.
Description
Type
RO
RO
14 Switch Loopback
R/W
When set, transmissions from the switch fabric MAC are not sent to the
external MII port. Instead, they are looped back into the switch engine.
From the MAC viewpoint, this is effectively a FAR LOOPBACK.
If loopback is enabled during half-duplex operation, then the Enable Receive
Own Transmit bit in the Port x MAC Receive Configuration Register
(MAC_RX_CFG_x) must be set for the port. Otherwise, the switch fabric will
ignore receive activity when transmitting in half-duplex mode.
Note: This mode works even if the Isolate (VPHY_ISO) bit of the Port x
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) is set.
13:11 RESERVED
RO
10 Turbo Mode Enable
R/W
When set, this bit changes the 100 Mbps data rate to 200 Mbps. The normal
Virtual PHY selection mechanism that chooses between 10 and 100 Mbps
will instead choose between 10 Mbps and 200 Mbps.
This is only effective in MII PHY mode. In RMII modes, the data rate remains
100Mbps or 10Mbps. In MAC mode, the external PHY determines the data
rate.
Note:
When operating at 200 Mbps, the drive strength of the MII output
clocks is selected using the RMII/Turbo MII Clock Strength bit.
When at 100 Mbps or 10 Mbps, the drive strength is fixed at
12 mA.
Default
-
Note 65
0b
-
Note 66
DS00001925A-page 200
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