LAN9353 Datasheet, PDF (514/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
20.6.4 POWER-ON AND CONFIGURATION STRAP TIMING
This diagram illustrates the configuration strap valid timing requirements in relation to power-on. In order for valid con-
figuration strap values to be read at power-on, the following timing requirements must be met.
FIGURE 20-5:
POWER-ON CONFIGURATION STRAP LATCHING TIMING
All External
Power Supplies
Configuration Straps
Vopp
t_cfg
TABLE 20-12: POWER-ON CONFIGURATION STRAP LATCHING TIMING VALUES
Symbol
Description
Min
Typ
Max Units
t_cfg
Configuration strap valid time
-
-
15
ms
Note: Configuration straps must only be pulled high or low. Configuration straps must not be driven as inputs.
Device configuration straps are also latched as a result of RST# assertion. Refer to Section 20.6.3, "Reset and Config-
uration Strap Timing" and Section 6.2.1, "Chip-Level Resets," on page 52 for additional details.
20.6.5 SMI SLAVE CONTROLLER I/O TIMING
Timing specifications for the SMI Slave Controller are given in Section 14.2.4, "SMI Timing Requirements," on page 381.
20.6.6 I²C SLAVE CONTROLLER I/O TIMING
The I²C Slave Controller adheres to the Philips I²C-Bus Specification. Refer to the Philips I²C-Bus Specification for
detailed I²C timing information. Refer to Section 11.0, "I2C Slave Controller," on page 340 for additional information on
the I²C Slave Controller.
20.6.7 PHY MANAGEMENT INTERFACE (PMI) I/O TIMING
Timing specifications for the PHY Management Interface (PMI) are given in Section 14.3.4, "PMI Timing Requirements,"
on page 383.
20.6.8 PHYSICAL PHY EXTERNAL MANAGEMENT ACCESS I/O TIMING
Timing specifications for Physical PHY External Management access are given in Section 9.2.19, "External Pin Access
Timing Requirements," on page 119.
20.6.9 VIRTUAL PHY MANAGEMENT ACCESS I/O TIMING
Timing specifications for Virtual PHY Management access are given in Section 9.3.4, "Virtual PHY Timing Require-
ments," on page 184.
20.6.10 I²C EEPROM I/O TIMING
Timing specifications for I²C EEPROM access are given in Section 12.3, "I2C Master EEPROM Controller," on
page 346.
20.6.11 MII / TURBO MII / RMII I/O TIMING
Timing specifications for the MII / Turbo MII and RMII interfaces are given in Section 13.4, "Switch Fabric Timing
Requirements," on page 366.
20.6.12 JTAG TIMING
Timing specifications for the JTAG interface are given in Table 19.1.1, “JTAG Timing Requirements,” on page 501.
DS00001925A-page 514
 2015 Microchip Technology Inc.