LAN9353 Datasheet, PDF (484/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
16.3.3 FREE RUNNING 25MHZ COUNTER REGISTER (FREE_RUN)
Offset:
09Ch
Size:
32 bits
This read-only register reflects the current value of the free-running 25MHz counter. Refer to Section 16.2, "Free-Run-
ning Clock," on page 481 for additional information.
Bits
Description
31:0 Free Running Counter (FR_CNT)
This field reflects the current value of the free-running 32-bit counter. At
reset, the counter starts at zero and is incremented by one every 25 MHz
cycle. When the maximum count has been reached, the counter will rollover
to zero and continue counting.
Note: The free running counter can take up to 160nS to clear after a reset
event.
Type
RO
Default
00000000h
DS00001925A-page 484
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