LAN9353 Datasheet, PDF (376/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
13.4.6 RMII INTERFACE TIMING (PHY MODE)
This section specifies the RMII interface timing when in PHY mode. Both input and output clock modes are specified.
FIGURE 13-11: RMII CLOCK OUTPUT MODE TIMING (PHY MODE)
Px_OUTCLK
(output)
t_clkp
t_clkh t_clkl
t_val
t_val
t_ohold
Px_OUTD[1:0]
t_ohold
Px_OUTDV
Px_IND[1:0],
Px_INER
t_ihold
Px_INDV
t_su t_ihold
t_su t_ihold
t_val
t_ihold
t_su
TABLE 13-11: RMII CLOCK OUTPUT MODE TIMING VALUES (PHY MODE)
Symbol
t_clkp
t_clkh
t_clkl
t_val
t_ohold
t_su
t_ihold
Description
Px_OUTCLK period
Px_OUTCLK high time
Px_OUTCLK low time
Px_OUTD[1:0], Px_OUTDV output valid from ris-
ing edge of Px_OUTCLK
Px_OUTD[1:0], Px_OUTDV output hold from ris-
ing edge of Px_OUTCLK
Px_IND[1:0], Px_INDV setup time to rising edge
of Px_INCLK
Px_IND[1:0], Px_INDV input hold time after ris-
ing edge of Px_INCLK
Min
20
t_clkp * 0.4
t_clkp * 0.4
-
3.0
4.0
1.5
Max
-
t_clkp * 0.6
t_clkp * 0.6
14.0
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
Note 11: Timing was designed for system load between 10 pF and 25 pF.
Notes
Note 11
Note 11
Note 11
Note 11
DS00001925A-page 376
 2015 Microchip Technology Inc.