LAN9353 Datasheet, PDF (41/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
5.0 REGISTER MAP
This chapter details the device register map and summarizes the various directly addressable System Control and Sta-
tus Registers (CSRs). Detailed descriptions of the System CSRs are provided in the chapters corresponding to their
function. Additional indirectly addressable registers are available in the various sub-blocks of the device. These regis-
ters are also detailed in their corresponding chapters.
Directly Addressable Registers
• Section 5.1, "System Control and Status Registers," on page 43
Indirectly Addressable Registers
• Section 9.2.20, "Physical PHY Registers," on page 120
• Section 10.7, "Switch Fabric Control and Status Registers," on page 246
Figure 5-1 contains an overall base register memory map of the device. This memory map is not drawn to scale, and
should be used for general reference only. Table 5-1 provides a summary of all directly addressable CSRs and their
corresponding addresses.
Note: Register bit type definitions are provided in Section 1.3, "Register Nomenclature," on page 7.
Not all device registers are memory mapped or directly addressable. For details on the accessibility of the
various device registers, refer the register sub-sections listed above.
 2015 Microchip Technology Inc.
DS00001925A-page 41