LAN9353 Datasheet, PDF (409/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Note: If the original correctionField contains a value of 7FFFFFFFFFFFFFFF, it is not modified.
If adjustment to the correctionField would result in a value that is larger than 7FFFFFFFFFFFFFFF, that
value is used instead.
The 1588 Port x RX Pdelay_Req Ingress Time Seconds Register (1588_RX_PDREQ_SEC_x) and the 1588 Port x RX
Pdelay_Req Ingress Time NanoSeconds Register (1588_RX_PDREQ_NS_x) hold the ingress time of the Pdelay_Req
message.
The 1588 Port x RX Pdelay_Req Ingress Correction Field High Register (1588_RX_PDREQ_CF_HI_x) and the 1588
Port x RX Pdelay_Req Ingress Correction Field Low Register (1588_RX_PDREQ_CF_LOW_x) hold the correctionField
of the Pdelay_Req message.
These registers are set by S/W prior to sending the Pdelay_Resp message or by the automatic updating described
above in PDELAY_REQ INGRESS TIME SAVING.
The egress time is the latency adjusted, 1588 Clock value, saved above at the start of the Pdelay_Resp frame.
Note: Since only four bits worth of seconds of the Pdelay_Req ingress time are stored, the Host must send the
Pdelay_Resp within 16 seconds.
This function is enabled via the TX PTP Pdelay_Resp Message Turnaround Time Insertion (TX_PTP_PDRE-
SP_TA_INSERT) bit in the 1588 Port x TX Modification Register (1588_TX_MOD_x) and is used only on frames which
have bit 7 of the PTP header’s reserved byte cleared.
As with Egress Time Insertion above:
• The versionPTP field of the PTP header is checked and the domainNumber field and alternateMasterFlag in the
flagField of the PTP header are not checked
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
CLEARING RESERVED FIELDS
If the frame is modified on egress for Correction Field Residence Time Adjustment:
• The reserved byte at the location specified by the TX PTP 1 Reserved Byte Offset (TX_PTP_1_RSVD_OFF-
SET[5:0]) is cleared.
• The four reserved bytes used for INGRESS TIME INSERTION INTO PACKETS are cleared if the TX PTP Clear
Four Byte Reserved Field (TX_PTP_CLR_4_RSVRD) bits in the 1588 Port x TX Modification Register (1588_TX-
_MOD_x) is set.
Note: The offset of the four reserved bytes is specified in TX PTP 4 Reserved Bytes Offset (TX_PTP_4_RS-
VD_OFFSET[5:0]).
FRAME UPDATING
Frames are modified even if their original FCS or UDP checksum is invalid.
• For IPv4, the UDP checksum is set to 0 under the following conditions.
If the TX PTP Clear UDP/IPv4 Checksum Enable (TX_PTP_CLR_UDPV4_CHKSUM) bit in the 1588 Port x TX
Modification Register 2 (1588_TX_MOD2_x) is set, the UDP checksum is set to 0 for Sync messages if Sync
Egress Time Insertion is enabled and for Pdelay_Resp messages if Pdelay_Resp Correction Field Turnaround
Time Adjustment is enabled. The ptp_version field is also checked.
• When Residence Time Correction is performed, the UDP checksum is already set to 0 by the ingress port.
• For IPv6, the two bytes beyond the end of the PTP message are modified to correct for the UDP checksum. These
bytes are updated by accumulating the differences between the original frame data and the substituted data using
the mechanism defined in IETF RFC 1624.
The existing two bytes are included in the calculation and are updated.
It is assumed that the original UDP checksum is valid and is not checked.
Note:
Since the two bytes beyond the end of the PTP message are modified based on the differences between
the original frame data and the substituted data, an invalid incoming checksum would result in an outgoing
checksum error.
Note: The two bytes beyond the end of the PTP message are located by using the messageLength field from the
PTP header.
• The frame FCS is recomputed
 2015 Microchip Technology Inc.
DS00001925A-page 409