LAN9353 Datasheet, PDF (120/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
FIGURE 9-8:
PHYSICAL PHY EXTERNAL ACCESS TIMING
MDC
t_val
t_ohold
MDIO
(Data-Out)
MDIO
(Data-In)
t_clkp
t_clkh t_clkl
t_ohold
t_su t_ihold
TABLE 9-12: PHYSICAL PHY EXTERNAL ACCESS TIMING VALUES
Symbol
Description
Min
Max
t_clkp
MDC period
400
-
t_clkh
MDC high time
160 (80%)
-
t_clkl
MDC low time
160 (80%)
-
t_val
MDIO output valid from rising edge of MDC
-
300
t_ohold
MDIO output hold from rising edge of MDC
10
-
t_su
MDIO input setup time to rising edge of MDC
10
-
t_ihold
MDIO input hold time after rising edge of MDC
5
-
Units
ns
ns
ns
ns
ns
ns
ns
Notes
Note 6
Note 6
Note 7
Note 7
Note 6: The Physical PHY design changes output data a nominal 4 clocks (25MHz) maximum and a nominal 2
clocks (25MHz) minimum following the rising edge of MDC.
Note 7: The Physical PHY design samples input data using the rising edge of MDC.
9.2.20 PHYSICAL PHY REGISTERS
The Physical PHYs A and B are comparable in functionality and have an identical set of non-memory mapped registers.
These registers are indirectly accessed through the PHY Management Interface Access Register (PMI_ACCESS) and
PHY Management Interface Data Register (PMI_DATA) or through the external MII management interface pins.
Because Physical PHY A and B registers are functionally identical, their register descriptions have been consolidated.
A lowercase “x” has been appended to the end of each PHY register name in this section, where “x” hold be replaced
with “A” or “B” for the PHY A or PHY B registers respectively. In some instances, a “1” or a “2” may be appropriate
instead.
A list of the MII serial accessible Control and Status registers and their corresponding register index numbers is included
in Table 9-13. Each individual PHY is assigned a unique PHY address as detailed in Section 9.1.1, "PHY Addressing,"
on page 94.
In addition to the MII serial accessible Control and Status registers, a set of indirectly accessible registers provides sup-
port for the IEEE 802.3 Section 45.2 MDIO Manageable Device (MMD) Registers. A list of these registers and their cor-
responding register index numbers is included in Table 9-19.
DS00001925A-page 120
 2015 Microchip Technology Inc.