LAN9353 Datasheet, PDF (394/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.0 IEEE 1588
15.1 Functional Overview
The device provides hardware support for the IEEE 1588-2008 Precision Time Protocol (PTP), allowing clock synchro-
nization with remote Ethernet devices, packet time stamping, and time driven event generation.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
Time stamping is supported on all ports, with an individual PTP Timestamp sub-module connected to each port. Any
port may function as a master or a slave clock per the IEEE 1588-2008 specification, and the device as a whole may
function as a transparent or boundary clock. Both end-to-end and peer-to-peer link delay mechanisms are supported as
are one-step and two-step operations.
A 32-bit seconds and 30-bit nanoseconds tunable clock is provided that is used as the time source for all PTP timestamp
related functions. A 1588 Clock Events sub-module provides 1588 Clock comparison based interrupt generation and
timestamp related GPIO event generation. GPIO pins can be used to trigger a timestamp capture when configured as
an input, or output a signal based on a 1588 Clock Target compare event.
All features of the IEEE 1588 unit can be monitored and configured via their respective configuration and status regis-
ters. A detailed description of all 1588 CSRs is included in Section 15.8, "1588 Registers".
15.1.1 IEEE 1588-2008
IEEE 1588-2008 specifies a Precision Time Protocol (PTP) used by master and slave clock devices to pass time infor-
mation in order to achieve clock synchronization. Ten network message types are defined:
• Sync
• Follow_Up
• Delay_Req
• Delay_Resp
• PDelay_Req
• PDelay_Resp
• PDelay_Resp_Follow_Up
• Announce
• Signaling
• Management
The first seven message types are used for clock synchronization. Using these messages, the protocol software may
calculate the offset and network delay between timestamps, adjusting the slave clock frequency as needed. Refer to
the IEEE 1588-2008 protocol for message definitions and proper usage.
A PTP domain is segmented into PTP sub-domains, which are then segmented into PTP communication paths. Within
each PTP communication path there is a maximum of one master clock, which is the source of time for each slave clock.
The determination of which clock is the master and which clock(s) is(are) the slave(s) is not fixed, but determined by
the IEEE 1588-2008 protocol. Similarly, each PTP sub-domain may have only one master clock, referred to as the
Grand Master Clock.
PTP communication paths are conceptually equivalent to Ethernet collision domains and may contain devices which
extend the network. However, unlike Ethernet collision domains, the PTP communication path does not stop at a net-
work switch, bridge, or router. This leads to a loss of precision when the network switch/bridge/router introduces a vari-
able delay. Boundary clocks are defined which conceptually bypass the switch/bridge/router (either physically or via
device integration). Essentially, a boundary clock acts as a slave to an upstream master, and as a master to a down
stream slave. A boundary clock may contain multiple ports, but a maximum of one slave port is permitted.
Although boundary clocks solve the issue of the variable delay influencing the synchronization accuracy, they add clock
jitter as each boundary clock tracks the clock of its upstream master. Another approach that is supported is the concept
of transparent clocks. These devices measure the delay they have added when forwarding a message (the residence
time) and report this additional delay either in the forwarded message (one-step) or in a subsequent message (two-
step).
The PTP relies on the knowledge of the path delays between the master and the slave. With this information, and the
knowledge of when the master has sent the packet, a slave can calculate its clock offset from the master and make
appropriate adjustments. There are two methods of obtaining the network path delay. Using the end-to-end method,
packets are exchanged between the slave and the master. Any intermediate variable bridge or switch delays are com-
DS00001925A-page 394
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