LAN9353 Datasheet, PDF (333/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.4.16 Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11)
Register #:
1C0Fh
Size:
32 bits
This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pac-
ing.
Bits
Description
31:26 RESERVED
25:13
Egress Rate Port 1 Priority Queue 1
These bits specify the egress data rate for the Port 1 priority queue 1. The
rate is specified in time per byte. The time is this value plus 1 times 20 ns.
12:0 Egress Rate Port 1 Priority Queue 0
These bits specify the egress data rate for the Port 1 priority queue 0. The
rate is specified in time per byte. The time is this value plus 1 times 20 ns.
Type
RO
R/W
R/W
Default
-
00000
00000000b
00000
00000000b
10.7.4.17 Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_12_13)
Register #:
1C10h
Size:
32 bits
This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pac-
ing.
Bits
Description
31:26
25:13
RESERVED
Egress Rate Port 1 Priority Queue 3
These bits specify the egress data rate for the Port 1 priority queue 3. The
rate is specified in time per byte. The time is this value plus 1 times 20 ns.
12:0 Egress Rate Port 1 Priority Queue 2
These bits specify the egress data rate for the Port 1 priority queue 2. The
rate is specified in time per byte. The time is this value plus 1 times 20 ns.
Type
RO
R/W
R/W
Default
-
00000
00000000b
00000
00000000b
 2015 Microchip Technology Inc.
DS00001925A-page 333