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| LAN9353 Datasheet, PDF (167/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII | |||
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LAN9353
9.2.20.33 PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x)
Index (In Decimal): 3.32865
Size:
16 bits
Bits
15:0 Physical Address [47:32]
Description
Type
R/W/
NASR
Note 30
Default
FFFFh
Note 30: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
ï£ 2015 Microchip Technology Inc.
DS00001925A-page 167
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