LAN9353 Datasheet, PDF (94/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.0 ETHERNET PHYS
9.1 Functional Overview
The device contains Physical PHYs A and B, and Virtual PHYs 0 and 1.
The A and B Physical PHYs are identical in functionality. Physical PHY A connects to the Switch Fabric Port 1. Physical
PHY B connects to Switch Fabric Port 2. These PHYs interface with their respective MAC via an internal MII interface.
Virtual PHY 0 provides the virtual functionality of a PHY and allows connection of an external MAC to Port 0 of the switch
fabric as if it was connected to a single port PHY. Virtual PHY 1 provides the virtual functionality of a PHY and allows
connection of an external MAC to Port 1 of the switch fabric as if it was connected to a single port PHY.
The Physical PHYs comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/
half duplex 100 Mbps (100BASE-TX / 100BASE-FX) or 10 Mbps (10BASE-T) Ethernet operation. All PHY registers fol-
low the IEEE 802.3 (clause 22.2.4) specified MII management register set and are fully configurable.
The device Ethernet PHYs are discussed in detail in the following sections:
• Section 9.2, "Physical PHYs A & B," on page 94
• Section 9.3, "Virtual PHYs 0 and 1," on page 181
9.1.1 PHY ADDRESSING
Each individual PHY is assigned a default PHY address via the phy_addr_sel_strap configuration strap as shown in
Table 9-1. Virtual PHYs 0 and 1 use the same address since they are on separate management interfaces.
In addition, the addresses for Physical PHY A and B can be changed via the PHY Address (PHYADD) field in the PHY
x Special Modes Register (PHY_SPECIAL_MODES_x). For proper operation, the addresses for Virtual PHY 0 and
Physical PHYs A and B must be unique. No check is performed to assure each PHY is set to a different address.
TABLE 9-1: DEFAULT PHY SERIAL MII ADDRESSING
phy_addr_sel_strap
0
1
Virtual PHY 0 and 1
Default
Address Value
0
1
PHY A Default
Address Value
1
2
PHY B Default
Address Value
2
3
9.2 Physical PHYs A & B
The device integrates two IEEE 802.3 PHY functions. The PHYs can be configured for either 100 Mbps copper
(100BASE-TX), 100 Mbps fiber (100BASE-FX) or 10 Mbps copper (10BASE-T) Ethernet operation and include Auto-
Negotiation and HP Auto-MDIX.
Note:
Because the Physical PHYs A and B are functionally identical, this section will describe them as the “Phys-
ical PHY x”, or simply “PHY”. Wherever a lowercase “x” has been appended to a port or signal name, it can
be replaced with “A” or “B” to indicate the PHY A or PHY B respectively. In some instances, a “1” or a “2”
may be appropriate instead. All references to “PHY” in this section can be used interchangeably for both
the Physical PHYs A and B.
9.2.1 FUNCTIONAL DESCRIPTION
Functionally, each PHY can be divided into the following sections:
• 100BASE-TX Transmit and 100BASE-TX Receive
• 10BASE-T Transmit and 10BASE-T Receive
• Auto-Negotiation
• HP Auto-MDIX
• PHY Management Control and PHY Interrupts
• PHY Power-Down Modes and Energy Efficient Ethernet
DS00001925A-page 94
 2015 Microchip Technology Inc.