LAN9353 Datasheet, PDF (207/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
RX LPI COUNTERS
The MAC maintains a counter, EEE RX LPI Transitions, that counts the number of times that the LPI indication from the
PHY changes from de-asserted to asserted. The counter is not writable and does not clear on read. The counter is reset
if the Energy Efficient Ethernet (EEE_ENABLE) bit in the Port x MAC Transmit Configuration Register (MAC_TX_CF-
G_x) is low.
The MAC maintains a counter, EEE RX LPI Time, that counts (in microseconds) the amount of time that the PHY indi-
cates LPI. The counter is not writable and does not clear on read. The counter is reset if the Energy Efficient Ethernet
(EEE_ENABLE) bit in the Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) is low.
10.3 Switch Engine (SWE)
The Switch Engine (SWE) is a VLAN layer 2 (link layer) switching engine supporting 3 ports. The SWE supports the
following types of frame formats: untagged frames, VLAN tagged frames and priority tagged frames. The SWE supports
both the 802.3 and Ethernet II frame formats.
The SWE provides the control for all forwarding/filtering rules. It handles the address learning and aging and the desti-
nation port resolution based upon the MAC address and VLAN of the packet. The SWE implements the standard bridge
port states for spanning tree and provides packet metering for input rate control. It also implements port mirroring, broad-
cast throttling and multicast pruning and filtering. Packet priorities are supported based on the IPv4 TOS bits and IPv6
Traffic Class bits using a DIFFSERV Table mapping, the non-DIFFSERV mapped IPv4 precedence bits, VLAN priority
using a per port Priority Regeneration Table, DA based static priority and Traffic Class mapping to one of 4 QoS transmit
priority queues.
The following sections detail the various features of the Switch Engine.
10.3.1 MAC ADDRESS LOOKUP TABLE
The Address Logic Resolution (ALR) maintains a 512 entry MAC Address Table. The ALR searches the table for the
destination MAC address. If the search finds a match, the associated data is returned indicating the destination port or
ports, whether to filter the packet, the packet’s priority (used if enabled) and whether to override the ingress and egress
spanning tree port state. Figure 10-1 displays the ALR table entry structure. Refer to the Switch Engine ALR Write Data
0 Register (SWE_ALR_WR_DAT_0) and the Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) for
detailed descriptions of these bits.
FIGURE 10-1:
ALR TABLE ENTRY STRUCTURE
Bit
58
57
56
55
54
53
52
51
50
49
4..8.
47
0
Valid
Age 1 /
Override
Static
Age 0 / Priority
Filter Enable
Priority
Port
MAC Address
10.3.1.1 Learning/Aging/Migration
The ALR adds new MAC addresses upon ingress along with the associated receive port.
If the source MAC address already exists, the entry is refreshed. This action serves two purposes. First, if the source
port has changed due to a network reconfiguration (migration), it is updated. Second, each instance the entry is
refreshed, the age status bits are set, keeping the entry active. Learning can be disabled per port via the Enable Learn-
ing on Ingress field of the Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG).
During each aging period, the ALR scans the learned MAC addresses. For entries which have an age status greater
than 0, the ALR decrements the age. As mentioned above, if a MAC address is subsequently refreshed, the age status
bits will be set again and the process would repeat. If a learned entry already had its age status bits decremented to 0
(by previous scans), the ALR will instead remove the learned entry. Four scans need to occur for a MAC address to be
aged and removed. Since the first scan could occur immediately following the add or refresh of an entry, an entry will
be aged and removed after a minimum of 3 age periods and a maximum of 4 age periods.
The minimum aging time is programmable using the Aging Time field of the Switch Engine ALR Configuration Register
(SWE_ALR_CFG) in 1 second increments from 1 second to approximately 69 minutes. The maximum aging time is 33%
higher.
The ALR Age Test bit in the Switch Engine ALR Configuration Register (SWE_ALR_CFG) changes the Aging Time from
seconds to milliseconds.
 2015 Microchip Technology Inc.
DS00001925A-page 207