LAN9353 Datasheet, PDF (151/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.21 PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
Index (decimal): 30
Size:
16 bits
This read/write register is used to enable or mask the various PHY interrupts and is used in conjunction with the PHY x
Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
Bits
Description
15:10 RESERVED
9
INT9_MASK
This interrupt mask bit enables/masks the Link Up (link status asserted) inter-
rupt.
0: Interrupt source is masked
1: Interrupt source is enabled
8
INT8_MASK
This interrupt mask bit enables/masks the WoL interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
7
INT7_MASK
This interrupt mask bit enables/masks the ENERGYON interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
6
INT6_MASK
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
5
INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
4
INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated)
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
3
INT3_MASK
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
-
0b
0b
0b
0b
0b
0b
0b
 2015 Microchip Technology Inc.
DS00001925A-page 151