LAN9353 Datasheet, PDF (163/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.30 PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x)
Index (In Decimal): 3.32785
Size:
16 bits
Bits
15
14
13:11
10
9
8
7:0
Description
Filter Enable
0 = Filter disabled
1 = Filter enabled
Filter Triggered
0 = Filter not triggered
1 = Filter triggered
RESERVED
Address Match Enable
When set, the destination address must match the programmed address.
When cleared, any unicast packet is accepted. Refer to Section 9.2.12.4,
"Wakeup Frame Detection," on page 110 for additional information.
Filter Any Multicast Enable
When set, any multicast packet other than a broadcast will cause an address
match. Refer to Section 9.2.12.4, "Wakeup Frame Detection," on page 110
for additional information.
Note: This bit has priority over bit 10 of this register.
Filter Broadcast Enable
When set, any broadcast frame will cause an address match. Refer to Sec-
tion 9.2.12.4, "Wakeup Frame Detection," on page 110 for additional informa-
tion.
Note: This bit has priority over bit 10 of this register.
Filter Pattern Offset
Specifies the offset of the first byte in the frame on which CRC checking
begins for Wakeup Frame recognition. Offset 0 is the first byte of the incom-
ing frame’s destination address.
Type
R/W/
NASR
Note 27
R/WC/
NASR
Note 27
RO
R/W/
NASR
Note 27
R/W/
NASR
Note 27
R/W/
NASR
Note 27
R/W/
NASR
Note 27
Default
0b
0b
-
0b
0b
0b
00h
Note 27: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
 2015 Microchip Technology Inc.
DS00001925A-page 163