LAN9353 Datasheet, PDF (137/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.11 PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA)
Index (In Decimal): 14
Size:
16 bits
This register in conjunction with the PHY x MMD Access Control Register (PHY_MMD_ACCESS) provides indirect
access to the MDIO Manageable Device (MMD) registers. Refer to the MDIO Manageable Device (MMD) Registers on
page 154 for additional details.
Bits
Description
15:0 MMD Register Address/Data
If the MMD Function field of the PHY x MMD Access Control Register
(PHY_MMD_ACCESS) is “00”, this field is used to indicate the MMD register
address to read/write of the device specified in the MMD Device Address
(DEVAD) field. Otherwise, this register is used to read/write data from/to the
previously specified MMD address.
Type
R/W
Default
0000h
 2015 Microchip Technology Inc.
DS00001925A-page 137