LAN9353 Datasheet, PDF (378/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
14.0 MII MANAGEMENT
14.1 Functional Overview
This chapter details the MII management functionality provided by the device, which includes the SMI Slave Controller,
the PHY Management Interface (PMI) and the MII Management Multiplexer.
The SMI Slave Controller is used for CPU management of the device via the MII pins and allows CPU access to all
system CSRs and the PHY Management Interface (PMI) is used to access the internal PHYs and optional external
PHYs, dependent on the mode of operation.
The MII Management Multiplexer is used to direct the connections of the MII management path based on the selected
mode of the device.
14.2 SMI Slave Controller
The SMI slave controller provides a serial slave interface for an external master to access the device’s internal registers.
The SMI slave controller uses the same pins and protocol as the IEEE 802.3 MII management function and differs only
in that SMI provides access to all internal registers by using a non-standard extended addressing map. The SMI protocol
co-exists with the MII management protocol by using the upper half of the PHY address space (16 through 31). All direct
and indirect registers can be accessed.
The SMI management mode is selected when the serial_mngt_mode_strap configuration strap is set to 0b.
14.2.1 DEVICE INITIALIZATION
Until the device has been initialized to the point where the various configuration inputs are valid, the SMI Slave will not
respond to or be affected by any external pin activity.
14.2.2 ACCESS DURING AND FOLLOWING POWER MANAGEMENT
During any power management mode other than D0, reads and writes are ignored and the SMI slave interface will not
respond to or be affected by any external pin activity.
14.2.3 SMI SLAVE COMMAND FORMAT
The MII management protocol is limited to 16-bit data accesses. The protocol is also limited to 5 PHY address bits and
5 register address bits. The SMI frame format can be seen in Table 14-1. The device uses the PHY Address field bits
3:0 as the system register address bits 9:6 and the Register Address field as the system register address bits 5:1. Reg-
ister Address field bit 0 is used as the upper/lower WORD select. The device requires two back-to-back accesses to
each register (with alternate settings of Register Address field bit 0) which are combined to form a 32-bit access. The
access may be performed in any order.
Note:
When accessing the device, the pair of cycles must be atomic. In this case, the first host SMI cycle is per-
formed to the low/high WORD and the second host SMI cycle is performed to the high/low WORD, forming
a 32-bit transaction with no cycles to the device in between. With the exception of Register Address field bit
0, all address and control bits must be the same for both 16-bit cycles of a 32-bit transaction.
Input data on the MDIO pin is sampled on the rising edge of the MDC input clock. Output data is sourced on the MDIO
pin with the rising edge of the clock. The MDIO pin is three-stated unless actively driving read data.
A read or a write is performed using the frame format shown in Table 14-1. All addresses and data are transferred MSB
first. Data bytes are transferred little endian. When Register Address bit 0 is 1, bytes 3 & 2 are selected with byte 3
occurring first. When Register Address bit 0 is 0, bytes 1 & 0 are selected with byte 1 occurring first.
DS00001925A-page 378
 2015 Microchip Technology Inc.