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| LAN9353 Datasheet, PDF (391/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII | |||
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LAN9353
14.4.1.5 Port 0 MAC Mode I2C Managed
In this mode, Physical PHYs A and B and the external PHY attached to the Port 0 MII pins are accessed by the PMI.
The PMI parallel interface is accessible via the I2C slave and the EEPROM Loader. The EEPROM Loader may access
PHYs A and B, as well as the external PHY, through the PMI registers. The Virtual PHY 0 parallel interface is accessible
via the SMI slave and the EEPROM Loader. However, this block is not used in this mode.
Figure 14-7 details the MII Mode Multiplexer management path connections for this mode.
FIGURE 14-7:
MII MUX MANAGEMENT PATH CONNECTIONS - MAC MODE I2C MANAGED
mdi SMI Slave
mdo
mdc
Parallel
Master
mdio_dir
mdi Virtual PHY 0
mdo
mdc
Parallel
Slave
mdio_dir
mdi PHY B
mdo
mdio_dir
mdc
mdi PHY A
mdo
mdio_dir
mdc
Management
Mode Selection
default =
MII pins
MII Pins
mdio_dir
p
mdo
i
n
mdi
m
mdc_dir
u
x
mdc_out
i
n
mdc_in
g
P0_MDIO
P0_MDC
Management
Mode Selection
mdo mdc mdi mdio_en_n
PMI
Parallel Slave
ï£ 2015 Microchip Technology Inc.
DS00001925A-page 391
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