LAN9353 Datasheet, PDF (476/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.46 1588 GPIO CAPTURE CONFIGURATION REGISTER (1588_GPIO_CAP_CONFIG)
Offset:
Bank:
15Ch
3
Size:
32 bits
Note:
Note:
Port and GPIO registers share a common address space. GPIO registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL).
The IEEE 1588 Unit supports 8 GPIO signals.
Bits
Description
31:24
Lock Enable GPIO Falling Edge (LOCK_GPIO_FE)
These bits enable/disables the GPIO falling edge lock. This lock prevents a
1588 capture from overwriting the Clock value if the GPIO interrupt in the
1588 Interrupt Status Register (1588_INT_STS) is already set due to a previ-
ous capture.
23:16
0: Disables GPIO falling edge lock
1: Enables GPIO falling edge lock
Lock Enable GPIO Rising Edge (LOCK_GPIO_RE)
These bits enable/disables the GPIO rising edge lock. This lock prevents a
1588 capture from overwriting the Clock value if the GPIO interrupt in the
1588 Interrupt Status Register (1588_INT_STS) is already set due to a previ-
ous capture.
0: Disables GPIO rising edge lock
1: Enables GPIO rising edge lock
15:8 GPIO Falling Edge Capture Enable 7-0
(GPIO_FE_CAPTURE_ENABLE[7:0])
These bits enable the falling edge of the respective GPIO input to capture the
1588 clock value and to set the respective 1588_GPIO interrupt in the 1588
Interrupt Status Register (1588_INT_STS).
0: Disables GPIO Capture
1: Enables GPIO Capture
Note:
The GPIO must be configured as an input for this function to
operate. GPIO inputs are edge sensitive and must be low for
greater than 40 ns to be recognized.
7:0 GPIO Rising Edge Capture Enable 7-0
(GPIO_RE_CAPTURE_ENABLE[7:0])
These bits enable the rising edge of the respective GPIO input to capture the
1588 clock value and to set the respective 1588_GPIO interrupt in the 1588
Interrupt Status Register (1588_INT_STS).
0: Disables GPIO Capture
1: Enables GPIO Capture
Note:
The GPIO must be configured as an input for this function to
operate. GPIO inputs are edge sensitive and must be high for
greater than 40 ns to be recognized.
Type
R/W
R/W
R/W
R/W
Default
FFh
FFh
00h
00h
DS00001925A-page 476
 2015 Microchip Technology Inc.