LAN9353 Datasheet, PDF (364/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
13.2.2.1 Reference Clock Selection
The 50 MHz RMII reference clock can be selected from either the P1_REFCLK pin input or the internal 50 MHz clock.
The choice is based on the setting of the RMII Clock Direction bit of the Port x Virtual PHY Special Control/Status Reg-
ister (VPHY_SPECIAL_CONTROL_STATUS_x). A low selects P1_REFCLK and a high selects the internal 50 MHz
clock. The high setting also enables P1_REFCLK as an output to be used as the reference clock to the PHY.
13.2.2.2 Clock Drive Strength
When P1_REFCLK is configured as an output via the RMII Clock Direction bit of the Port x Virtual PHY Special Control/
Status Register (VPHY_SPECIAL_CONTROL_STATUS_x), its drive strength is based on the setting of the RMII/Turbo
MII Clock Strength bit of the Port x Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STA-
TUS_x). A low selects 12 mA, a high selects 16 mA.
13.2.3 PORT 1 RMII PHY MODE
When operating in RMII PHY mode, the MII Data Interface mimics the operation of an RMII PHY and is used when inter-
facing to an external MAC that does not support the full MII interface. The RMII interface uses a subset of the MII pins.
The P1_OUTD[1:0], P1_OUTDV, P1_IND[1:0], P1_INDV and P1_REFCLK pins are the only MII pins used to commu-
nicate with the external MAC in this mode. This mode provides loopback test capabilities for the Switch Fabric and exter-
nal MAC, as well as collision testing for the Switch Fabric.
Note: The RMII standard does not support collision testing for the external MAC.
13.2.3.1 Isolate
When in RMII PHY mode, if the Isolate (VPHY_ISO) bit of the Port x Virtual PHY Basic Control Register (VPHY_BA-
SIC_CTRL_x) is set, RMII data path output pins are three-stated, the pull-ups and pull-downs are disabled and the RMII
data path input pins are ignored (disabled into the non-active state and powered down). Setting the Isolate (VPHY_ISO)
bit does not cause isolation of the MII management pins and does not affect RMII MAC mode.
13.2.3.2 Reference Clock Selection
The 50 MHz RMII reference clock can be selected from either the P1_REFCLK pin input or the internal 50 MHz clock.
The choice is based on the setting of the RMII Clock Direction bit of the Port x Virtual PHY Special Control/Status Reg-
ister (VPHY_SPECIAL_CONTROL_STATUS_x). A low selects P1_REFCLK and a high selects the internal 50 MHz
clock. The high setting also enables P1_REFCLK as an output to be used as the reference clock to the MAC.
13.2.3.3 Clock Drive Strength
When P1_REFCLK is configured as an output via the RMII Clock Direction bit of the Port x Virtual PHY Special Control/
Status Register (VPHY_SPECIAL_CONTROL_STATUS_x), its drive strength is based on the setting of the RMII/Turbo
MII Clock Strength bit of the Port x Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STA-
TUS_x). A low selects 12 mA, a high selects 16 mA.
13.2.3.4 Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal is not generated when operating in RMII PHY mode. The SQEOFF bit of the Port x Virtual
PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS_x) has no effect when operating in RMII
PHY mode.
13.2.3.5 Collision Test
External MAC collision testing is not available when operating in the RMII PHY mode. The Collision Test
(VPHY_COL_TEST) bit of the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) has no effect on sys-
tem operation in RMII PHY mode.
Switch Fabric collision testing is available and is enabled when the Switch Collision Test bit of the Port x Virtual PHY
Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS_x) is set. In this test mode, any transmissions
from the Switch Fabric will result in the assertion of an internal collision signal to the Switch Fabric Port 1. Switch Fabric
collision test occurs regardless of the setting of the Isolate (VPHY_ISO) bit.
13.2.3.6 Loopback Mode
Two forms of loopback testing are available: External MAC loopback and Switch Fabric loopback.
DS00001925A-page 364
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