LAN9353 Datasheet, PDF (78/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 7-1: SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
FD_FC_strap_0
(cont.)
Description
Pin / Default Value
Port 0 Virtual PHY Full-Duplex Flow Control Enable Strap: 1b
This strap affects the default value of the following register bits
(x=0):
manual_FC_strap_0
EEE_enable_strap_0
• Asymmetric Pause and Pause bits of the Port x Virtual
PHY Auto-Negotiation Link Partner Base Page Ability
Register (VPHY_AN_LP_BASE_ABILITY_x)
Refer to the respective register definition sections for addi-
tional information.
Port 0 Virtual PHY Manual Flow Control Enable Strap: This 0b
strap affects the default value of the following register bits
(x=0):
• Asymmetric Pause and Symmetric Pause bits of the Port
x Virtual PHY Auto-Negotiation Advertisement Register
(VPHY_AN_ADV_x)
Refer to the respective register definition sections for addi-
tional information.
Switch Port 0 Energy Efficient Ethernet Enable Strap:
0b
Configures the default value of the Energy Efficient Ethernet
(EEE_ENABLE) bit in the (x=0) Port x MAC Transmit Configu-
ration Register (MAC_TX_CFG_x).
Refer to the respective register definition sections for addi-
tional information.
7.2 Hard-Straps
Hard-straps are latched upon Power-On Reset (POR) or pin reset (RST#) only. Unlike soft-straps, hard-straps always
have an associated pin and cannot be overridden by the EEPROM Loader. These straps are used as either direct con-
figuration values or as register defaults. Table 7-2 provides a list of all hard-straps and their associated pin. These
straps, along with their pin assignments are also fully defined in Section 3.0, "Pin Descriptions and Configuration," on
page 10.
TABLE 7-2: HARD-STRAP CONFIGURATION STRAP DEFINITIONS
Strap Name
eeprom_size_strap
serial_mngt_mode_strap
Description
Pins
EEPROM Size Strap: Configures the EEPROM size range. E2PSIZE
A low selects 1K bits (128 x 8) through 16K bits (2K x 8).
A high selects 32K bits (4K x 8) through 512K bits (64K x 8).
Serial Management Mode Strap: Configures the serial
management mode.
MNGT0
0 = SMI Managed Mode
1 = I²C Managed Mode
Refer to Section 2.0, "General Description," on page 8 for
additional information on the various modes of the device.
DS00001925A-page 78
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