LAN9353 Datasheet, PDF (189/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.3.5.2 Port x Virtual PHY Basic Status Register (VPHY_BASIC_STATUS_x)
Offset:
PORT0: 1C4h
PORT1: 0C4h
Index (decimal): 1
Size:
This register is used to monitor the status of the Virtual PHY.
32 bits
16 bits
Bits
Description
31:16 RESERVED
(See Note 39)
15 100BASE-T4
This bit displays the status of 100BASE-T4 compatibility.
0: PHY not able to perform 100BASE-T4
1: PHY able to perform 100BASE-T4
14 100BASE-X Full Duplex
This bit displays the status of 100BASE-X full duplex compatibility.
0: PHY not able to perform 100BASE-X full duplex
1: PHY able to perform 100BASE-X full duplex
13 100BASE-X Half Duplex
This bit displays the status of 100BASE-X half duplex compatibility.
0: PHY not able to perform 100BASE-X half duplex
1: PHY able to perform 100BASE-X half duplex
12 10BASE-T Full Duplex
This bit displays the status of 10BASE-T full duplex compatibility.
0: PHY not able to perform 10BASE-T full duplex
1: PHY able to perform 10BASE-T full duplex
11 10BASE-T Half Duplex
This bit displays the status of 10BASE-T half duplex compatibility.
0: PHY not able to perform 10BASE-T half duplex
1: PHY able to perform 10BASE-T half duplex
10 100BASE-T2 Full Duplex
This bit displays the status of 100BASE-T2 full duplex compatibility.
0: PHY not able to perform 100BASE-T2 full duplex
1: PHY able to perform 100BASE-T2 full duplex
9
100BASE-T2 Half Duplex
This bit displays the status of 100BASE-T2 half duplex compatibility.
0: PHY not able to perform 100BASE-T2 half duplex
1: PHY able to perform 100BASE-T2 half duplex
Type
RO
RO
Default
-
0b
Note 40
RO
1b
RO
1b
RO
1b
RO
1b
RO
0b
Note 40
RO
0b
Note 40
 2015 Microchip Technology Inc.
DS00001925A-page 189