LAN9353 Datasheet, PDF (130/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Bits
Description
5
10BASE-T Half Duplex
This bit determines the advertised 10BASE-T half duplex capability.
0: 10BASE-T half duplex ability not advertised
1: 10BASE-T half duplex ability advertised
4:0 Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
Type
R/W
Default
Note 13
Table 9-15
R/W
00001b
00001: IEEE 802.3
Note 11: The default values of the Asymmetric Pause and Symmetric Pause bits are determined by the Manual Flow
Control Enable Strap (manual_FC_strap_1 for PHY A, manual_FC_strap_2 for PHY B). When the Manual
Flow Control Enable Strap is 0, the Symmetric Pause bit defaults to 1 and the Asymmetric Pause bit defaults
to the setting of the Full-Duplex Flow Control Enable Strap (FD_FC_strap_1 for PHY A, FD_FC_strap_2 for
PHY B). When the Manual Flow Control Enable Strap is 1, both bits default to 0. Refer to Section 7.0, "Con-
figuration Straps," on page 67 for more information. In 100BASE-FX mode, the default value of these bits is
0.
Note 12: The default value of this bit is determined by the logical OR of the Auto-Negotiation Enable strap
(autoneg_strap_1 for PHY A, autoneg_strap_2 for PHY B) with the logical AND of the negated Speed Select
strap (speed_strap_1 for PHY A, speed_strap_2 for PHY B) and the Duplex Select Strap (duplex_strap_1
for PHY A, duplex_strap_2 for PHY B). Table 9-14 defines the default behavior of this bit. Refer to Section
7.0, "Configuration Straps," on page 67 for more information. In 100BASE-FX mode, the default value of this
bit is a 0.
TABLE 9-14: 10BASE-T FULL DUPLEX ADVERTISEMENT DEFAULT VALUE
autoneg_strap_x speed_strap_x
duplex_strap_x Default 10BASE-T Full Duplex (Bit 6) Value
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
x
x
1
Note 13: The default value of this bit is determined by the logical OR of the Auto-Negotiation strap (autoneg_strap_1
for PHY A, autoneg_strap_2 for PHY B) and the negated Speed Select strap (speed_strap_1 for PHY A,
speed_strap_2 for PHY B). Table 9-15 defines the default behavior of this bit. Refer to Section 7.0, "Config-
uration Straps," on page 67 for more information. In 100BASE-FX mode, the default value of this bit is a 0.
TABLE 9-15: 10BASE-T HALF DUPLEX ADVERTISEMENT BIT DEFAULT VALUE
autoneg_strap_x
0
0
1
1
speed_strap_x
0
1
0
1
Default 10BASE-T Half Duplex (Bit 5) Value
1
0
1
1
DS00001925A-page 130
 2015 Microchip Technology Inc.