LAN9353 Datasheet, PDF (206/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
CLIENT LPI REQUESTS TO MAC
When the TX FIFO is empty for a time (in microseconds) specified in Port x EEE TX LPI Request Delay Register
(EEE_TX_LPI_REQ_DELAY_x), a TX LPI request is asserted to the MAC. A setting of 0 us is possible for this time. If
the TX FIFO becomes not empty while the timer is running, the timer is reset (i.e. empty time is not cumulative). Once
TX LPI is requested and the TX FIFO becomes not empty, the TX LPI request is negated.
The TX FIFO empty timer is reset if Energy Efficient Ethernet (EEE_ENABLE) in the Port x MAC Transmit Configuration
Register (MAC_TX_CFG_x) is cleared.
TX LPI requests are asserted only if the Energy Efficient Ethernet (EEE_ENABLE) bit is set, and when appropriate, if
the current speed is 100 Mbps, the current duplex is full and the auto-negotiation result indicates that both the local and
partner device support EEE 100 Mbps. In order to prevent an unstable link condition, the PHY link status also must indi-
cate “up” for one second before LPI is requested.
These tests for the allowance of TX LPI are done in the Switch Fabric Interface Logic block. See Section 10.5.2, "EEE
Enable Logic," on page 228 for further details.
TX LPI requests are asserted even if the TX Enable (TXEN) bit in the Port x MAC Transmit Configuration Register
(MAC_TX_CFG_x) is cleared.
MAC LPI REQUEST TO PHY
Lower Power Idle (LPI) is requested by the MAC to the PHY using the MII value of TXEN=0, TXER=1,
TXD[3:0]=4’b0001.
The MAC always finishes the current packet before signaling TX LPI to the PHY.
The MAC will generate TX LPI requests to the PHY even if the TX Enable (TXEN) bit in the Port x MAC Transmit Con-
figuration Register (MAC_TX_CFG_x) is cleared.
802.3az specifies the usage of a simplified full duplex MAC with carrier sense deferral. Basically this means that once
the TX LPI request to the PHY is de-asserted, the MAC will defer the time specified in Port x EEE Time Wait TX System
Register (EEE_TW_TX_SYS_x) in addition to the normal IPG before sending a frame.
TX LPI COUNTERS
The MAC maintains a counter, EEE TX LPI Transitions, that counts the number of times that TX LPI request to the PHY
changes from de-asserted to asserted. The counter is not writable and does not clear on read. The counter is reset if
the Energy Efficient Ethernet (EEE_ENABLE) bit in the Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)
is low.
The MAC maintains a counter, EEE TX LPI Time, that counts (in microseconds) the amount of time that TX LPI request
to the PHY is asserted. Note that this counter does not include the time specified in the Port x EEE Time Wait TX System
Register (EEE_TW_TX_SYS_x). The counter is not writable and does not clear on read. The counter is reset if the
Energy Efficient Ethernet (EEE_ENABLE) bit in the Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) is
low.
10.2.3.2 RX LPI Detection
Receive Lower Power Idle (LPI) is indicated by the PHY to the MAC using the MII value of RXDV=0, RXER=1,
TXD[3:0]=4’b0001.
DECODING LPI
The MAC will decode the LPI indication only when Energy Efficient Ethernet (EEE_ENABLE) is set in the Port x MAC
Transmit Configuration Register (MAC_TX_CFG_x), and when appropriate, the current speed is 100Mbs, the current
duplex is full and the auto-negotiation result indicates that both the local and partner device supports EEE at 100Mbs.
In order to prevent an unstable link condition, the PHY link status also must indicate “up” for one second before LPI is
decoded.
These tests for the allowance of TX LPI are done in the Switch Fabric Interface Logic block. See Section 10.5.2, "EEE
Enable Logic," on page 228 for further details.
The MAC will decode the LPI indication even if RX Enable (RXEN) in the Port x MAC Receive Configuration Register
(MAC_RX_CFG_x) is cleared.
DS00001925A-page 206
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