LAN9353 Datasheet, PDF (71/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 7-1: SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
Description
Pin / Default Value
duplex_strap_1
(cont.)
Port 1 Virtual PHY Duplex Select Strap: This strap affects 1b
the default value of the following bits in the (x=1) Port x Virtual
Note: duplex_strap_1 and ^{PHY Auto-Negotiation Link Partner Base Page Ability Regis-}
duplex_pol_strap_1 share ^{ter (VPHY_AN_LP_BASE_ABILITY_x):}
the same strap register and
EEPROM bit.
• 100BASE-X Full Duplex
• 100BASE-X Half Duplex
• 10BASE-T Full Duplex
• 10BASE-T Half Duplex
Refer to Section 9.3.5.6 and Table 9-23 for more information.
Refer to the respective register definition sections for addi-
tional information.
duplex_pol_strap_1
Switch Port 1 Duplex Polarity Strap: This strap determines 1b
Note: duplex_strap_1 and ^{the polarity of the P1_DUPLEX pin when in Port 1 MII MAC}
duplex_pol_strap_1 share ^{and RMII MAC modes.}
the same strap register and
EEPROM bit.
0 = P1_DUPLEX low means full-duplex
1 = P1_DUPLEX high means full-duplex
BP_EN_strap_1
Refer to the respective register definition sections for addi-
tional information.
Switch Port 1 Backpressure Enable Strap: Configures the 1b
default value for the Port 1 Backpressure Enable (BP_EN_1)
bit of the Port 1 Manual Flow Control Register (MANUAL_F-
C_1).
FD_FC_strap_1
Refer to the respective register definition sections for addi-
tional information.
Switch Port 1 Full-Duplex Flow Control Enable Strap: This 1b
strap is used to configure the default value of the following
register bits:
• Port 1 Full-Duplex Transmit Flow Control Enable (TX_F-
C_1) and Port 1 Full-Duplex Receive Flow Control Enable
(RX_FC_1) bits of the Port 1 Manual Flow Control Regis-
ter (MANUAL_FC_1)
FD_FC_strap_1
(cont.)
Refer to the respective register definition sections for addi-
tional information.
PHY A Full-Duplex Flow Control Enable Strap: This strap 1b
affects the default value of the following register bits (x=A):
• Asymmetric Pause bit of the PHY x Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x)
Note: This has no effect when the PHY is in 100BASE-FX
mode.
Refer to the respective register definition sections for addi-
tional information.
 2015 Microchip Technology Inc.
DS00001925A-page 71