LAN9353 Datasheet, PDF (485/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
17.0 GPIO/LED CONTROLLER
17.1 Functional Overview
The GPIO/LED Controller provides 8 configurable general purpose input/output pins, GPIO[7:0]. These pins can be indi-
vidually configured to function as inputs, push-pull outputs or open drain outputs and each is capable of interrupt gen-
eration with configurable polarity. Alternatively, 6 GPIO pins can be configured as LED outputs, enabling these pins to
drive Ethernet status LEDs for external indication of various attributes of the ports. All GPIOs also provide extended
1588 functionality. Refer to Section 15.5, "1588 GPIOs," on page 413 for additional details.
GPIO and LED functionality is configured via the GPIO/LED System Control and Status Registers (CSRs). These reg-
isters are defined in Section 17.4, "GPIO/LED Registers," on page 489.
17.2 GPIO Operation
The GPIO controller is comprised of 8 programmable input/output pins. These pins are individually configurable via the
GPIO CSRs. On application of a chip-level reset:
• All GPIOs are set as inputs (GPIO Direction 7-0 (GPIODIR[7:0]) cleared in General Purpose I/O Data & Direction
Register (GPIO_DATA_DIR))
• All GPIO interrupts are disabled (GPIO Interrupt Enable[7:0] (GPIO[7:0]_INT_EN) cleared in General Purpose I/O
Interrupt Status and Enable Register (GPIO_INT_STS_EN)
• All GPIO interrupts are configured to low logic level triggering (GPIO Interrupt/1588 Polarity 7-0 (GPIO_POL[7:0])
cleared in General Purpose I/O Configuration Register (GPIO_CFG))
Note: GPIO[5:0] may be configured as LED outputs by default, dependent on the LED_en_strap[5:0] configuration
straps. Refer to Section 17.3, "LED Operation" for additional information.
The direction and buffer type of all GPIOs are configured via the General Purpose I/O Configuration Register (GPI-
O_CFG) and General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). The direction of each GPIO, input or
output, should be configured first via its respective GPIO Direction 7-0 (GPIODIR[7:0]) bit in the General Purpose I/O
Data & Direction Register (GPIO_DATA_DIR). When configured as an output, the output buffer type for each GPIO is
selected by the GPIO Buffer Type 7-0 (GPIOBUF[7:0]) bits in the General Purpose I/O Configuration Register (GPI-
O_CFG). Push/pull and open-drain output buffers are supported for each GPIO. When functioning as an open-drain
driver, the GPIO output pin is driven low when the corresponding GPIO Data 7-0 (GPIOD[7:0]) bit in the General Pur-
pose I/O Data & Direction Register (GPIO_DATA_DIR) is cleared to 0 and is not driven when set to 1.
When a GPIO is enabled as a push/pull output, the value output to the GPIO pin is set via the corresponding GPIO Data
7-0 (GPIOD[7:0]) bit in the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). For GPIOs configured
as inputs, the corresponding GPIO Data 7-0 (GPIOD[7:0]) bit reflects the current state of the GPIO input.
In GPIO mode, the input buffers are disabled when the pin is set to an output and the pull-ups are normally enabled.
Note:
Upon reset, GPIOs that were outputs may generate an active interrupt status as the system settles - typically
when a low GPIO pin slowly rises due to the internal pull-up. The interrupt status bits within the General
Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) should be cleared as part of the
device initialization software routine.
17.2.1 GPIO INTERRUPTS
Each GPIO provides the ability to trigger a unique GPIO interrupt in the General Purpose I/O Interrupt Status and Enable
Register (GPIO_INT_STS_EN). Reading the GPIO Interrupt[7:0] (GPIO[7:0]_INT) bits of this register provides the cur-
rent status of the corresponding interrupt and each interrupt is enabled by setting the corresponding GPIO Interrupt
Enable[7:0] (GPIO[7:0]_INT_EN) bit. The GPIO/LED Controller aggregates the enabled interrupt values into an internal
signal that is sent to the System Interrupt Controller and is reflected via the Interrupt Status Register (INT_STS) GPIO
Interrupt Event (GPIO) bit. For more information on interrupts, refer to Section 8.0, "System Interrupts," on page 84.
As interrupts, GPIO inputs are level sensitive and must be active for greater than 40 ns to be recognized.
17.2.1.1 GPIO Interrupt Polarity
The interrupt polarity can be set for each individual GPIO via the GPIO Interrupt/1588 Polarity 7-0 (GPIO_POL[7:0]) bits
in the General Purpose I/O Configuration Register (GPIO_CFG). When set, a high logic level on the GPIO pin will set
the corresponding interrupt bit in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN).
When cleared, a low logic level on the GPIO pin will set the corresponding interrupt bit.
 2015 Microchip Technology Inc.
DS00001925A-page 485